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參數(shù)資料
| 型號(hào)： | MCM69L820AZP9.5R |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 4M Late Write 2.5 V I/O |
| 中文描述： | 256K X 18 CACHE SRAM, 9.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 212K |
| 代理商： | MCM69L820AZP9.5R |
MCM69L738A
MCM69L820A
11
MOTOROLA FAST SRAM
FUNCTIONAL OPERATION
READ AND WRITE OPERATIONS
All control signals except G are registered on the rising
edge of the CK clock. These signals must meet the setup
and hold times shown in the AC Characteristics table. On the
falling edge of the current cycle, the output latch becomes
transparent and data is available. The output data is latched
on the rising edge of the next clock. The output data is
available at the output at tKLQV or tKHQV, whichever is
later. tKHQV is the internal latency of the device. During this
same cycle a new read address can be applied to the
address pins.
A write cycle can occur on the next cycle as long as tKLQX
and tDVKH are met. Read cycles may follow write cycles
immediately.
G, SS, and SW control output drive. Chip deselect via a
high on SS at the rising edge of the CK clock has its effect on
the output drivers immediately. SW low deselects the output
drivers immediately (on the same cycle). Output selecting via
a low on SS and high on SW at a rising CK clock has its ef-
fect on the output drivers at tKLQX. Output drive is also con-
trolled directly by output enable, G. G is an asynchronous
input. No clock edges are required to enable or disable the
output with G.
Output data will be valid the later of tGLQV, tKHQV, or
tKLQV. Outputs will begin driving at tKLQX1. Outputs will
hold previous data until tKLQX or tGHQX.
WRITE AND BYTE WRITE FUNCTIONS
Note that in the following discussion the term “byte” refers
to nine bits of the RAM I/O bus. In all cases, the timing pa-
rameters described for synchronous write input (SW) apply
to each of the byte write enable inputs (SBa, SBb, etc.).
Byte write enable inputs have no effect on read cycles.
This allows the system designer not interested in performing
byte writes to connect the byte enable inputs to active low
(VSS). Reads of all bytes proceed normally and write cycles,
activated via a low on SW, and the rising edge of the CK
clock, write the entire RAM I/O width. This way the designer
is spared having to drive multiple write input buffer loads.
Byte writes are performed using the byte write enable
inputs in conjunction with the synchronous write input (SW).
It is important to note that writing any one byte will inhibit a
read of all bytes at the current address. The RAM can not
simultaneously read one byte and write another at the same
address. A write cycle initiated with none of the byte write en-
able inputs active is neither a read or a write. No write will
occur, but the outputs will be deselected as in a normal write
cycle.
LATE WRITE
The write address is sampled on the first rising edge of
clock and write data is sampled on the following rising edge.
The late write feature is implemented with single stage
write buffering. Write buffering is transparent to the user. A
comparator monitors the address bus and, when necessary,
routes buffer contents to the outputs to assure coherent op-
eration. This occurs in all cases whether there is a byte write
or a full word is written.
POWER UP AND INITIALIZATION
Please note, per the Absolute Maximum Ratings table,
VDDQ is not to exceed VDD + 0.5 V, whatever the
instantaneous value of VDD. Once supplies have reached
specification levels, a minimum dwell of 1.0
μ
s with CK clock
inputs cycling is required before beginning normal
operations.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCM69L738AZP9R | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT07; No. of Contacts:6; Connector Shell Size:10; Connecting Termination:Solder; Circular Shell Style:Jam Nut Receptacle; Body Style:Straight |
| MCM69L820AZP9R | Circular Connector; Body Material:Aluminum; Series:PT07; Number of Contacts:6; Connector Shell Size:10; Connecting Termination:Solder; Circular Shell Style:Jam Nut Receptacle; Circular Contact Gender:Socket; Insert Arrangement:10-6 |
| MCM69L738AZP8.5R | Circular Connector; Body Material:Aluminum; Series:PT07; No. of Contacts:12; Connector Shell Size:14; Connecting Termination:Solder; Circular Shell Style:Jam Nut Receptacle; Circular Contact Gender:Pin; Insert Arrangement:14-12 |
| MCM69L820AZP8.5R | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT07; No. of Contacts:12; Connector Shell Size:14; Connecting Termination:Solder; Circular Shell Style:Jam Nut Receptacle |
| MCM69L738A | 4M Late Write 2.5 V I/O |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM69L820AZP9R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write 2.5 V I/O |
| MCM69P536C | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM69P536CTQ4 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM69P536CTQ4.5 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM69P536CTQ4.5R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
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