參數(shù)資料
型號(hào): MCM63Z818
廠商: Motorola, Inc.
英文描述: 256Kx18 Bit Synchronous Fast Static RAM(256Kx18位同步快速靜態(tài)RAM)
中文描述: 256Kx18位同步快速靜態(tài)存儲(chǔ)器(256Kx18位同步快速靜態(tài)內(nèi)存)
文件頁數(shù): 6/20頁
文件大?。?/td> 135K
代理商: MCM63Z818
MCM63Z736 MCM63Z818
6
MOTOROLA FAST SRAM
TRUTH TABLE
CK
CKE
E
SW
SBx
ADV
SA0 –
SAx
Next Operation
Input Command
Code
Notes
L–H
1
X
X
X
X
X
Hold
H
1, 2
L–H
0
False
X
X
0
X
Deselect
D
1, 2
L–H
0
True
0
V
0
V
Load Address, New Write
W
1, 2, 3,
4, 5
L–H
0
True
1
X
0
V
Load Address, New Read
R
1, 2
L–H
0
X
X
V (W)
1
X
Burst
B
1, 2, 4,
6 7
6, 7
X (R, D)
Continue
NOTES:
1. X = don‘t care, 1 = logic high, 0 = logic low, V = valid signal, according to AC Operating Conditions and Characteristics.
2. E = true if SE1 and SE3 = 0, and SE2 = 1.
3. Byte write enables, SBx are evaluated only as new write addresses are loaded.
4. No control inputs except CKE, SBx, and ADV are recognized in a clock cycle where ADV is sampled high.
5. A write with SBx not valid does load addresses.
6. A burst write with SBx not valid does increment address.
7. ADV controls whether the RAM enters burst mode. If the previous cycle was a write, then ADV = 1 results in a burst write. If the previous
cycle is a read, then ADV = 1 results in a burst read. ADV = 1 will also continue a deslect cycle.
WRITE TRUTH TABLE
Cycle Type
SW
SBa
SBb
SBc
(See Note 1)
SBd
(See Note 1)
Read
H
X
X
X
X
Write Byte a
L
L
H
H
H
Write Byte b
L
H
L
H
H
Write Byte c (See Note 1)
L
H
H
L
H
Write Byte d (See Note 1)
L
H
H
H
L
Write All Bytes
L
L
L
L
L
NOTE:
1. Valid only for MCM63Z736.
LINEAR BURST ADDRESS TABLE
(LBO = VSS)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . . X00
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE
(LBO = VDD)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X10
X . . . X01
X . . . X00
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