參數(shù)資料
型號: MCM6205DJ15R2
廠商: MOTOROLA INC
元件分類: SRAM
英文描述: 32K x 9 Bit Fast Static RAM
中文描述: 32K X 9 STANDARD SRAM, 15 ns, PDSO32
封裝: 0.300 INCH, PLASTIC, SOJ-32
文件頁數(shù): 5/8頁
文件大?。?/td> 143K
代理商: MCM6205DJ15R2
MCM6205D
5
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled, See Notes 1, 2, and 3)
MCM6205D–15
MCM6205D–20
MCM6205D–25
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Units
Notes
Write Cycle Time
tAVAV
tAVWL
tAVWH
tWLWH,
tWLEH
15
20
25
ns
4
Address Setup Time
0
0
0
ns
Address Valid to End of Write
12
15
20
ns
Write Pulse Width
12
15
20
ns
Write Pulse Width, G High
tWLWH,
tWLEH
10
12
15
ns
5
Data Valid to End of Write
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
7
8
10
ns
Data Hold Time
0
0
0
ns
Write Low to Output High–Z
0
7
0
8
0
10
ns
6, 7, 8
Write High to Output Active
4
4
4
ns
6, 7, 8
Write Recovery Time
0
0
0
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. If G goes low coincident with or after W goes low, the output will remain in a high impedance state.
4. All timings are referenced from the last valid address to the first transitioning address.
5. If G
VIH, the output will remain in a high impedance state.
6. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device.
7. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1B.
8. This parameter is sampled and not 100% tested.
WRITE CYCLE 1
(W Controlled, See Notes 1, 2, and 3)
DATA VALID
tDVWH
tAVWL
tAVWH
tAVAV
tWHAX
tWLWH
tWLEH
tWHDX
tWLQZ
tWHQX
HIGH–Z
HIGH–Z
A (ADDRESS)
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
相關(guān)PDF資料
PDF描述
MCM6205DJ20 32K x 9 Bit Fast Static RAM
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