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參數(shù)資料
| 型號(hào)： | MCM44F64 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 1MB R4000 Secondary Cache Fast Static RAM Module Set |
| 中文描述： | 1MB的二級(jí)高速緩存R4000的快速靜態(tài)存儲(chǔ)器模塊集 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大小： | 103K |
| 代理商： | MCM44F64 |
MCM4464 SERIES
7
MOTOROLA FAST SRAM
WRITE CYCLE 2
(DCS or TCS Controlled, See Notes 1 and 2)
–12
–15
–17
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Address Setup Time
tAVEL
tA0VEL
tAVEH
tA0VEH
tELEH,
tELWH
0
—
0
—
0
—
ns
A0 Setup Time
0
—
0
—
0
—
ns
Address Valid to End of Write
12
—
15
—
17
—
ns
A0 Valid to End of Write
10
—
12
—
14
—
ns
Data/Tag Enable to End of Write
12
—
15
—
17
—
ns
Data Valid to End of Write
tDVEH
tEHDX
tEHAX
tEHA0X
6
—
7
—
8
—
ns
Data Hold Time
5
—
5
—
5
—
ns
Write Recovery Time
5
—
5
—
5
—
ns
Write Recovery Time – A0
5
—
5
—
5
—
ns
NOTES:
1. A write occurs during the overlap of DCS or TCS low and WE low.
2. Enable timings are the same for both DCS and TCS.
WRITE CYCLE 2
tEHDX
tDVEH
tEHAX
tELWH
tELEH
tAVEL
DATA VALID
HIGH–Z
WE (WRITE ENABLE)
DCS/TCS
(DATA/TAG ENABLE)
Q (DATA OUT)
D (DATA IN)
A1 – A15
tAVEH
A0
tEHA0X
tA0VEL
tA0VEH
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