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參數(shù)資料
| 型號： | MCM44F64 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 1MB R4000 Secondary Cache Fast Static RAM Module Set |
| 中文描述： | 1MB的二級高速緩存R4000的快速靜態(tài)存儲器模塊集 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 103K |
| 代理商： | MCM44F64 |
MCM4464 SERIES
6
MOTOROLA FAST SRAM
WRITE CYCLE 1
(WE Controlled, See Notes 1 and 2)
–12
–15
–17
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Address Setup Time
tAVWL
tA0VWL
tAVWH
tA0VWH
tWLWH
tWLEH
5
—
5
—
5
—
ns
A0 Setup Time
0
—
0
—
0
—
ns
Address Valid to End of Write
12
—
15
—
17
—
ns
A0 Valid to End of Write
10
—
12
—
14
—
ns
Write Pulse Width
7
—
10
—
12
—
ns
Data Valid to End of Write
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
tWHA0X
6
—
7
—
8
—
ns
Data Hold Time
0
—
0
—
0
—
ns
Write Low to Data High–Z
0
4
0
5
0
6
ns
3, 4
Write High to Output Active
3
—
3
—
3
—
ns
3, 4
Write Recovery Time
0
—
0
—
0
—
ns
Write Recovery Time – A0
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of DCS or TCS low and WE low.
2. Enable timings are the same for both DCS and TCS.
3. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
4. This parameter is sampled and not 100% tested.
WRITE CYCLE 1
tA0VWL
DATA VALID
tAVWH
tWHDX
tWLQZ
tWHQX
HIGH–Z
A1 – A15
WE (WRITE ENABLE)
DCS/TCS
(DATA/TAG ENABLE)
Q (DATA OUT)
D (DATA IN)
tWLEH
tWHAX
tAVWL
A0
tWLWH
tDVWH
tWHA0X
tA0VWH
HIGH–Z
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