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參數(shù)資料
| 型號： | MCM44C64 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 1MB R4000 Secondary Cache Fast Static RAM Module Set |
| 中文描述： | 1MB的二級高速緩存R4000的快速靜態(tài)存儲器模塊集 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 103K |
| 代理商： | MCM44C64 |
MCM4464 SERIES
4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
3 ns
Output Timing Measurement Reference Level
Output Load
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . .
See Figure 1A
READ CYCLE
(See Notes 1 and 2)
–12
–15
–17
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Address Access Time
tAVQV
tA0QV
tELQV
tGLQV
tAXQX
tA0XQX
tELQX
tEHQZ
tGLQX
tGHQZ
—
12
—
15
—
17
ns
A0 Access Time
—
10
—
12
—
14
ns
Data/Tag Enable Access Time
—
12
—
15
—
17
ns
Output Enable Access Time
—
9
—
10
—
11
ns
Output Hold from Address Change
4
—
4
—
4
—
ns
Output Hold from A0 Change
4
—
4
—
4
—
ns
Data/Tag Enable Low to Output Active
2
—
2
—
2
—
ns
3, 4
Data/Tag Enable High to Output High–Z
1
9
1
10
1
11
ns
3, 4
Output Enable Low to Output Active
1
—
1
—
1
—
ns
3, 4
Output Enable High to Output High–Z
1
9
1
10
1
11
ns
3, 4
NOTES:
1. WE is high for read cycle.
2. Enable timings are the same for both DCS and TCS.
3. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
4. This parameter is sampled and not 100% tested.
OUTPUT
Z0 = 50
RL = 50
VL = 1.5 V
Figure 1A
Figure 1B
5 pF
+5 V
OUTPUT
255
480
AC TEST LOADS
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never pro-
vides data later than that time.
TIMING LIMITS
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