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參數(shù)資料
| 型號： | MCM20027IBBL |
| 廠商： | MOTOROLA INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Color SXGA Digital Image Sensor 1280 x 1024 pixel progressive scan solid state image sensor with integrated CDS/PGA/ADC, digital programming, control |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CQCC48 |
| 封裝： | CERAMIC, LCC-48 |
| 文件頁數(shù)： | 61/74頁 |
| 文件大?。?/td> | 973K |
| 代理商： | MCM20027IBBL |
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MOTOROLA, INC. 2001
Revision 8.0 - 28 November 2001 : MCM20027
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
61
ImageMOS
The
Pixel Data Stream Control Register
allows the user to select how the output pixel data stream is encoded/for-
matted.
The
vcb
bit allows the user to force all the Blanking data coming out of the A2D to be 0.
The
vcg
bit allows the user to choose between encoded pixel data output stream or non-encoded pixel data output
stream.
The
vcc
bit allows the user to clip the output active pixel data to lie between 001 and 3FE
The default mode (
Normal Mode)
has the SOF, HCLK, VCLK etc. signals being utilised to indicate the start of data
and the end of data. (
Figure 2, on page 7
and
Figure 14, on page 20
)
Register Value =
00
h
Another mode,
Video Mode
is a mode where the SOF and Row start/end signals are encoded (contained) in the
Active Pixel data stream. In addition, all data that is not a SOF, Row start/end, or Active pixel data are forced to 0.
i.e. all Blanking data from the A2D are forced to 0. The following sequence identifies the signals below: (see
Figure
, on page 30
)
a) SOF (1st Row of Pixel Data) - “3FF x 4)
b) Start of all other Rows - “3FF x 2” then “000 x 2”
2 - 0
HCLK
Delay
Delay = ((hckd[d]-4)x 0.5) - 16 MCLKs
100
b
Address
64
h
HCLK Control
Default
5C
h
msb (7)
6
5
4
3
2
1
lsb (0)
x
FUO
FUO
FUO
FUO
hckd[2]
hckd[1]
hckd[0]
Table 52. HCLK Delay Register
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