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參數(shù)資料
| 型號： | MCM20027IBBL |
| 廠商： | MOTOROLA INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Color SXGA Digital Image Sensor 1280 x 1024 pixel progressive scan solid state image sensor with integrated CDS/PGA/ADC, digital programming, control |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CQCC48 |
| 封裝： | CERAMIC, LCC-48 |
| 文件頁數(shù)： | 27/74頁 |
| 文件大?。?/td> | 973K |
| 代理商： | MCM20027IBBL |
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Revision 8.0 - 28 November 2001 : MCM20027
MOTOROLA
27
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
If the master receiver does not acknowledge the slave
transmitter after a byte transmission, it means 'end of
data' to the slave, so the slave releases the SDATA line
for the master to generate STOP or START signal.
10.6 Stop Signal
The master can terminate the communication by gener-
ating a STOP signal to free the bus. However, the mas-
ter may generate a START signal followed by a calling
command without generating a STOP signal first. This
is called a Repeated START. A STOP signal is defined
as a low-to-high transition of SDATA while SCLK is at
logical “1” (see
Figure 17
).
The master can generate a STOP even if the slave has
generated an acknowledge bit at which point the slave
must release the bus.
10.7 Repeated START Signal
A Repeated START signal is a START signal generated
without first generating a STOP signal to terminate the
communication. This is used by the master to commu-
nicate with another slave or with the same slave in a dif-
ferent mode (transmit/receive mode) without releasing
the bus.
As shown in
Figure 18
, a Repeated START signal is be-
ing used during the read cycle and to redirect the data
transfer from a write cycle (master transmits the register
address to the slave) to a read cycle (slave transmits
the data from the designated register to the slave).
Figure 17. WRITE Cycle using I2C Bus
10.8 I2C Bus Clocking and Synchronization
Open drain outputs are used on the SCLK outputs of all
master and slave devices so that the clock can be syn-
chronized and stretched using wire-AND logic. This
means that the slowest device will keep the bus from
going faster than it is capable of receiving or transmit-
ting data.
After the master has driven SCLK from High to Low, all
the slaves drive SCLK Low for the required period that
is needed by each slave device and then releases the
SCLK bus. If the slave SCLK Low period is greater than
the master SCLK Low period, the resulting SCLK bus
signal Low period is stretched. Therefore, synchronized
clocking occurs since the SCLK is held low by the de-
vice with the longest Low period. Also, this method can
be used by the slaves to slow down the bit rate of a
transfer. The master controls the length of time that the
SCLK line is in the High state. The data on the SDATline
is valid when the master switches the SCLK line from a
High to a Low.
Slave devices may hold the SCLK low after completion
of one byte transfer (9 bits). In such case, it halts the bus
clock and forces the master clock into wait states until
the slave releases the SCLK line.
SCLK
1
2
3
4
5
6
7
8
MSB
1
2
3
4
5
6
7
8
MSB
LSB
9
9
1
2
3
4
5
6
7
8
MSB
LSB
D7 D6 D5 D4 D3 D2 D1 D0
9
Ack
Bit
from
Data to write MCM20027 Register
Stop
Signal
MCM20027
SCLK
SDATA
SDATA
Start
Signal
Ack
Bit
from
AD7 AD6 AD5 AD4 AD3 AD2 AD1
“0”
“1”
“0”
“1”
D7
D6 D5
D4 D3 D2 D1 D0
MCM20027 I
2
C Bus Address
MCM20027 Register Address
Write
MCM20027
Ack
Bit
from
MCM20027
“0”
“1” “1”
LSB
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