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| 型號： | MCM20027 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Color SXGA Digital Image Sensor 1280 x 1024 pixel progressive scan solid state image sensor with integrated CDS/PGA/ADC, digital programming, control |
| 中文描述： | 彩色SXGA數(shù)字圖像傳感器1280 × 1024像素逐行掃描固態(tài)集成信用違約掉圖像傳感器/美國PGA /模數(shù)轉(zhuǎn)換器，數(shù)字節(jié)目，控制 |
| 文件頁數(shù)： | 30/74頁 |
| 文件大?。?/td> | 973K |
| 代理商： | MCM20027 |
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MOTOROLA
Revision 8.0 - 28 November 2001 : MCM20027
30
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Figure 19. I
2
C SERIAL INTERFACE
6
TIMING SPECIFICATIONS
I
2
C SERIAL INTERFACE
6
TIMING SPECIFICATIONS
(see
Figure 19
)
Symbol
Characteristic
Min
Max
Unit
f
max
SCLK maximum frequency
50
400
KHz
M1
Start condition SCLK hold time
4
-
T
MCLK7
M2
SCLK low period
8
-
T
MCLK
M3
SCLK/SDATA rise time [from V
IL
= (0.2)*VDD to V
IH
= (.8)*VDD]
-
.3
μ
s
8
M4
SDATA hold time
4
-
T
MCLK7
M5
SCLK/SDATA fall time (from Vh = 2.4V to Vl = 0.5V)
-
.3
μ
s
8
M6
SCLK high period
4
-
T
MCLK
M7
SDATA setup time
4
-
T
MCLK7
M8
Start / Repeated Start condition SCLK setup time
4
-
T
MCLK
M9
Stop condition SCLK setup time
4
-
T
MCLK
C
I
Capacitive for each I/O pin
-
10
pF
Cbus
Capacitive bus load for SCLK and SDATA
-
200
pF
Rp
Pull-up Resistor on SCLK and SDATA
1.5
10
k
9
6
I
2
C is a proprietary Phillips interface bus
7
The unit T
MCLK
is the period of the input master clock; The frequency of MCLK is assumed 13.5 MHz
8
The capacitive load is 200 pF
9
A pull-up resistor to VDD is required on each of the SCLK and SDATA lines; for a maximum bus capacitive load of 200 pf, the minimum
value of Rp should be selected in order to meet specifications
M1
SCLK
M3
M5
V
IH
V
IL
M2
M6
SDATA
M4
M7
M8
M9
M8
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