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| 型號： | MCM20027 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Color SXGA Digital Image Sensor 1280 x 1024 pixel progressive scan solid state image sensor with integrated CDS/PGA/ADC, digital programming, control |
| 中文描述： | 彩色SXGA數(shù)字圖像傳感器1280 × 1024像素逐行掃描固態(tài)集成信用違約掉圖像傳感器/美國PGA /模數(shù)轉(zhuǎn)換器，數(shù)字節(jié)目，控制 |
| 文件頁數(shù)： | 15/74頁 |
| 文件大小： | 973K |
| 代理商： | MCM20027 |
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Revision 8.0 - 28 November 2001 : MCM20027
MOTOROLA
15
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
7.0 Analog Signal Processing Chain Overview
The MCM20027’s analog signal processing (ASP)
chain incorporates Correlated Double Sampling (CDS),
Frame Rate Clamp (FRC), two Digitally Programmable
Gain Amplifiers (DPGA), Offset Correction (DOVA), and
a 10-bit Analog to Digital Converter (ADC).
To see a pictorial depiction of this chain refer to
“Speci-
fications” on page 2
7.1 Correlated Double Sampling (CDS)
The uncertainty associated with the reset action of a ca-
pacitive node results in a reset noise which is equal to
kTC; C being the capacitance of the node, T the temper-
ature and k the Boltzmann constant. A common way of
eliminating this noise source in all image sensors is to
use Correlated Double Sampling. The output signal is
sampled twice, once for its reset (reference) level and
once for the actual video signal. These values are sam-
pled and held while a difference amplifier subtracts the
reference level from the signal output. Double sampling
of the signal eliminates correlated noise sources (see
.
“Conceptual block diagram of CDS implementation.”
on page 15
)
Figure 12. Conceptual block diagram of CDS
implementation.
7.2 Frame Rate Clamp (FRC)
The FRC (
Figure 13
) is designed to provide a feed for-
ward dark level subtract reference level measurement.
In the automatic FRC mode, the optical black level ref-
erence is re-established each time the image sensor
begins a new frame. The MCM20027 uses optical black
(dark) pixels to aid in establishing this reference.
Figure 13. FRC Conceptual Block Diagram
On the MCM20027, dark pixel input signals should be
sampled for a minimum of 137
μ
s to allow the two 0.1
μ
F
capacitors at the CLRCA and CLRCB pins sufficient
time to charge for 10-bit accuracy. This guarantees that
the FRC’s “droop” will be maintained at <750
μ
V
,
thus
assuring the specified ADC 10-bit accuracy at +0.5
LSB. Therefore, at maximum operational frequency
(13.5 MHz), the imager would require a number of
frames to establish the dark pixel reference for subse-
quent active pixel processing. The dark pixel sample
period is automatically controlled internally and it is set
to skip the first 3 dark rows and then sample the next 2
dark rows. When “dark clamping” is active, each dark
pixel is processed and held to establish pixel reference
level at the CLRCA and CLRCB pins. During this period,
the FRC’s differential outputs (V+ and V- on the Diff
Amp,
Figure 13
) are clamped to V
cm
. Together, these
actions help to eliminate the dark level offset, simulta-
neously establishing the desired zero code at the ADC
output.
Care should be exercised in choosing the capacitors for
the CLRCA, B pins to reflect different frame rates.
The user can disable this function via the
FRC Definition
Register; Table 54
and the
Power Configuration Regis-
ter, (Table 19), on page 41
(Check this - should be re-
ferring o FRC clamp ON/OFF) which will allow the ASP
chain to drift in offset Per-Column Digital Offset Voltage
Adjust (DOVA), and controls the number of rows to
clamp on.
AMP
S/H1
S/H2
CDSP1
CDSP2
AVIN
V+
V-
+
-
V+
V-
BUF
1X
FRC
V
cm
CLRCA
V
cm
Cap
LRCA
0.1
μ
LRCLMP
LRCLMP
+
BUF
-
1X
CLRCB
Cap
LRCB
0.1
μ
LRCLMP
LRCLMP
Previous
+
-
LRCLMP
V
cm
LRCLMP
Stage
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