參數(shù)資料
型號(hào): MCL908QT1
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: M68HC08 Microcontrollers
中文描述: M68HC08系列微控制器
文件頁(yè)數(shù): 81/182頁(yè)
文件大小: 1603K
代理商: MCL908QT1
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)當(dāng)前第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)
Functional Description
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
81
Figure 9-2. Keyboard Interrupt Block Diagram
If the MODEK bit is set, the keyboard interrupt inputs are both falling edge and low-level sensitive, and
both of the following actions must occur to clear a keyboard interrupt request:
Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the interrupt request. Software may generate the interrupt acknowledge signal by writing a 1 to the
ACKK bit in the keyboard status and control register (KBSCR). The ACKK bit is useful in
applications that poll the keyboard interrupt inputs and require software to clear the keyboard
interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also
prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on
the keyboard interrupt inputs. A falling edge that occurs after writing to the ACKK bit latches
another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the central
processor unit (CPU) loads the program counter with the vector address at locations $FFE0 and
$FFE1.
Return of all enabled keyboard interrupt inputs to logic 1 — As long as any enabled keyboard
interrupt pin is at logic 0, the keyboard interrupt remains set. The auto wakeup interrupt input,
AWUIREQ, will be cleared only by writing to ACKK bit in KBSCR or reset.
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur
in any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge sensitive only. With MODEK clear, a
vector fetch or software clear immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a
keyboard interrupt input stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending
interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes
it useful in applications where polling is preferred.
KBIE0
KBIE5
.
.
.
D
Q
CK
CLR
V
DD
MODEK
IMASKK
KEYBOARD
INTERRUPT FF
VECTOR FETCH
DECODER
ACKK
INTERNAL BUS
RESET
KBI5
KBI0
SYNCHRONIZER
KEYF
KEYBOARD
INTERRUPT
REQUEST
TO PULLUP ENABLE
AWUIREQ
(1)
TO PULLUP ENABLE
1. For AWUGEN logic refer to
Figure 4-1. Auto Wakeup Interrupt
Request Generation Logic
.
相關(guān)PDF資料
PDF描述
MCM63R836 MCM63R836
MCN51-30S3-PFA 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor
MCN51-30S3-DS 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor
MCR100-3 SCR
MCR100-8 Silicon Controlled Rectifiers(Reverse Blocking Triode Thyristors)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCL908QT1CDWE 功能描述:8位微控制器 -MCU LO V-1.5K FLASH W/O AD RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
MCL908QT1CDWER 功能描述:8位微控制器 -MCU LO V-1.5K FLASH W/O ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
MCL908QT1DWE 功能描述:8位微控制器 -MCU LO V-1.5K FLASH W/O ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
MCL908QT2 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC08 Microcontrollers
MCL908QT2CDWE 功能描述:8位微控制器 -MCU LO V-1.5K FLASH W/ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT