參數(shù)資料
型號(hào): MCIMX31VKN5B
廠商: Freescale Semiconductor
文件頁數(shù): 115/122頁
文件大?。?/td> 0K
描述: IC MPU MAP I.MX31 457-MAPBGA
標(biāo)準(zhǔn)包裝: 152
系列: i.MX31
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,ATA,EBI/EMI,F(xiàn)IR,I²C,MMC/SD,PCMCIA,SIM,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,LCD,POR,PWM,WDT
程序存儲(chǔ)器類型: ROMless
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.22 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 457-LFBGA
包裝: 托盤
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
92
Freescale Semiconductor
Electrical Characteristics
Figure 74. Internal-Reset Card Reset Sequence
4.3.20.2.2
Cards with Active Low Reset
The sequence of reset for this kind of card is as follows (see Figure 75):
1. After powerup, the clock signal is enabled on CLK (time T0)
2. After 200 clock cycles, RX must be high.
3. RST must remain Low for at least 40000 clock cycles after T0 (no response is to be received on
RX during those 40000 clock cycles)
4. RST is set High (time T1)
5. RST must remain High for at least 40000 clock cycles after T1 and a response must be received
on RX between 400 and 40000 clock cycles after T1.
Figure 75. Active-Low-Reset Card Reset Sequence
SVEN
CLK
RX
2
T0
1
response
2
1
< 200 clock cycles
< 40000 clock cycles
400 clock cycles <
SVEN
CLK
RX
2
T0
1
response
RST
T1
1
2
< 200 clock cycles
< 40000 clock cycles
400 clock cycles <
3
400000 clock cycles <
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX31
Product
Family
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