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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MCIMX31VKN5B |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 104/122闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC MPU MAP I.MX31 457-MAPBGA |
| 妯欐簴鍖呰锛� | 152 |
| 绯诲垪锛� | i.MX31 |
| 鏍稿績铏曠悊鍣細 | ARM11 |
| 鑺珨灏哄锛� | 32-浣� |
| 閫熷害锛� | 532MHz |
| 閫ｉ€氭€э細 | 1 绶�锛孉TA锛孍BI/EMI锛孎(xi脿n)IR锛孖²C锛孧MC/SD锛孭CMCIA锛孲IM锛孲PI锛孲SI锛孶ART/USART锛孶SB锛孶SB OTG |
| 澶栧湇瑷�(sh猫)鍌欙細 | DMA锛孡CD锛孭OR锛孭WM锛學DT |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | ROMless |
| RAM 瀹归噺锛� | 16K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.22 V ~ 3.3 V |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 457-LFBGA |
| 鍖呰锛� | 鎵樼洡 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�鐣跺墠绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
82
Freescale Semiconductor
Electrical Characteristics
4.3.15.5.4
Serial Interfaces, Electrical Characteristics
Figure 65 depicts timing of the serial interface. Table 51 lists the timing parameters at display access level.
Figure 65. Asynchronous Serial Interface Timing Diagram
Table 51. Asynchronous Serial Interface Timing Parameters鈥擜ccess Level
ID
Parameter
Symbol
Min.
Typ.1
Max.
Units
IP48 Read system cycle time
Tcycr
Tdicpr鈥�1.5
Tdicpr2
Tdicpr+1.5
ns
IP49 Write system cycle time
Tcycw
Tdicpw鈥�1.5
Tdicpw3
Tdicpw+1.5
ns
IP50 Read clock low pulse width
Trl
Tdicdr鈥揟dicur鈥�1.5
Tdicdr4鈥揟dicur5
Tdicdr鈥揟dicur+1.5
ns
IP51 Read clock high pulse width
Trh
Tdicpr鈥揟dicdr+Tdicur鈥�1.5
Tdicpr鈥揟dicdr+
Tdicur
Tdicpr鈥揟dicdr+Tdicur+1.5
ns
IP52 Write clock low pulse width
Twl
Tdicdw鈥揟dicuw鈥�1.5
Tdicdw6鈥揟dicuw7
Tdicdw鈥揟dicuw+1.5
ns
IP53 Write clock high pulse width
Twh
Tdicpw鈥揟dicdw+
Tdicuw鈥�1.5
Tdicpw鈥揟dicdw+
Tdicuw
Tdicpw鈥揟dicdw+
Tdicuw+1.5
ns
IP54 Controls setup time for read
Tdcsr
Tdicur鈥�1.5
Tdicur
鈥�
ns
IP55 Controls hold time for read
Tdchr
Tdicpr鈥揟dicdr鈥�1.5
Tdicpr鈥揟dicdr
鈥�
ns
IP49, IP48
Read Data
IP51, IP53
IP58
IP59
DISPB_SER_RS
DISPB_DATA
(Input)
(Output)
IP56,IP54
IP57, IP55
IP50, IP52
IP61
IP60
IP67,IP65
IP47
IP64, IP66
IP62, IP63
DISPB_SD_D_CLK
read point
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX31
Product
Family
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