參數(shù)資料
型號: MCIMX27MOP4A
廠商: Freescale Semiconductor
文件頁數(shù): 106/152頁
文件大?。?/td> 0K
描述: IC MPU I.MX27 19X19 473MAPBGA
標準包裝: 84
系列: i.MX27
核心處理器: ARM9
芯體尺寸: 32-位
速度: 400MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設備: DMA,LCD,POR,PWM,WDT
程序存儲器類型: ROMless
RAM 容量: 45K x 8
電壓 - 電源 (Vcc/Vdd): 1.38 V ~ 1.52 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 473-LFBGA
包裝: 托盤
i.MX27 and i.MX27L Data Sheet, Rev. 1.8
Freescale Semiconductor
57
Electrical Characteristics
4.3.2
Fast Ethernet Controller (FEC)
This section describes the AC timing specifications of the FEC. The MII signals are compatible with
transceivers operating at a voltage of 3.3 V.
4.3.2.1
MII Receive Signal Timing (FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER,
and FEC_RX_CLK)
The receiver functions correctly up to a FEC_RX_CLK maximum frequency of 25 MHz + 1%. There is
no minimum frequency requirement. In addition, the FEC IPG clock frequency must exceed twice the
FEC_RX_CLK frequency.
Figure 17 shows the MII receive signal timings, and Table 25 lists the timing parameters.
Figure 17. MII Receive Signal Timing Diagram
Table 24. DMAC Timing Parameters
Parameter
Description
3.0 V
1.8 V
Unit
WCS
BCS
WCS
BCS
Tmin_assert
Minimum assertion time of External Grant signal
8hclk+8.6
8hclk+2.74
8hclk+7.17
8hclk+3.25
ns
Tmax_req_assert Maximum External Request assertion time after
assertion of Grant signal
9hclk–20.66
9hclk–6.7
9hclk–17.96
9hclk–8.16
ns
Tmax_read
Maximum External Request assertion time after
first read completion
8hclk–6.21
8hclk–0.77
8hclk–5.84
8hclk–0.66
ns
Tmax_write
Maximum External Request assertion time after
first write completion
3hclk–5.87
3hclk–8.83
3hclk–15.9
3hclkv91.2
ns
Table 25. MII Receive Signal Timing Parameters
ID
Parameter1
Min
Max
Unit
M1
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
5
ns
M2
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
5
ns
M3
FEC_RX_CLK pulse width high
35%
65%
FEC_RX_CLK period
FEC_RX_CLK (input)
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER
M3
M4
M1
M2
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