參數(shù)資料
型號: MCIMX257CJN4A
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA347
封裝: 12 X 12 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-347
文件頁數(shù): 63/154頁
文件大小: 1498K
代理商: MCIMX257CJN4A
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
16
Freescale Semiconductor
3.2
Supply Power-Up/Power-Down Requirements and Restrictions
Any i.MX25 board design must comply with the power-up and power-down sequence guidelines given in
this section to ensure reliable operation of the device. Recommended power-up and power-down
sequences are given in the following subsections.
CAUTION
Deviations from the guidelines in this section may result in the following
situations:
Excessive current during power-up phase
Prevention of the device from booting
Irreversible damage to the i.MX25 (worst-case scenario)
NOTE
For security applications, the coin battery must be connected during both
power-up and power-down sequences to ensure that security keys are not
unintentionally erased.
3.2.1
Power-Up Sequence
The following power-up sequence is recommended:
1. Assert power on reset (POR).
2. Turn on digital logic domain and I/O power supplies VDDn and NVCCx.
3. Turn on all other analog power supplies, including USBPHY1_VDDA_BIAS,
USBPHY1_UPLL_VDD, USBPHY1_VDDA, USBPHY2_VDD, OSC24M_VDD,
MPPLL_VDD, UPLL_VDD, NVCC_ADC, and FUSEVDD (FUSEVDD is tied to GND if fuses
are not being programmed). The minimum time between turning on each power supply is the time
it takes for the previous supply to be stable.
4. Negate the POR signal.
NOTE
The user is advised to connect FUSEVDD to GND except when fuses
are being programmed, in order to prevent unintentional blowing of
fuses.
Other power-up sequences may be possible; however, the above
sequence has been verified and is recommended.
There is a 1-ms minimum time between supplies coming up, and a 1-ms
minimum time between POR_B assert and deassert.
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