參數(shù)資料
型號: MCIMX257CJN4A
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA347
封裝: 12 X 12 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-347
文件頁數(shù): 140/154頁
文件大小: 1498K
代理商: MCIMX257CJN4A
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
86
Freescale Semiconductor
3.7.9
Fast Ethernet Controller (FEC) Timing
The FEC is designed to support both 10- and 100-Mbps Ethernet networks compliant with the IEEE 802.3
standard. An external transceiver interface and transceiver function are required to complete the interface
to the media. The FEC supports 10/100 Mbps MII (18 pins altogether), 10/100 Mbps RMII (ten pins,
including serial management interface) and the 10-Mbps-only 7-Wire interface (which uses seven of the
MII pins), for connection to an external Ethernet transceiver. All signals are compatible with transceivers
operating at a voltage of 3.3 V.
The following subsections describe the timing for MII and RMII modes.
3.7.9.1
FEC MII Mode Timing
The following subsections describe MII receive, transmit, asynchronous inputs, and serial management
signal timings.
3.7.9.1.4
MII Receive Signal Timing (FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and
FEC_RX_CLK)
The receiver functions correctly up to an FEC_RX_CLK maximum frequency of 25 MHz + 1%. There is
no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the
FEC_RX_CLK frequency.
Figure 55 shows MII receive signal timings. Table 62 describes the timing parameters (M1–M4) shown in
the figure.
Figure 55. MII Receive Signal Timing Diagram
1 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
Table 62. MII Receive Signal Timing
ID
Characteristic1
Min.
Max.
Unit
M1
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
5
ns
M2
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
5
ns
M3
FEC_RX_CLK pulse width high
35%
65%
FEC_RX_CLK period
M4
FEC_RX_CLK pulse width low
35%
65%
FEC_RX_CLK period
FEC_RX_CLK (input)
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER
M3
M4
M1
M2
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