參數(shù)資料
型號(hào): MCF54416CMJ250
廠商: Freescale Semiconductor
文件頁數(shù): 35/61頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 256MAPBGA
標(biāo)準(zhǔn)包裝: 450
系列: MCF5441x
核心處理器: Coldfire V4
芯體尺寸: 32-位
速度: 250MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,智能卡,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,PWM,WDT
輸入/輸出數(shù): 87
程序存儲(chǔ)器類型: ROMless
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.14 V ~ 1.32 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
包裝: 托盤
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical characteristics
Freescale Semiconductor
40
4.16.1
General timing requirements
Figure 21 shows the timing of the SIM module, and Table 22 lists the timing parameters.
Figure 21. SIM clock timing diagram
4.16.2
Reset sequence
4.16.2.1
Cards with internal reset
The reset sequence for this kind of SIM card is as follows (see Figure 22):
After powerup, the clock signal is enabled on SIM_CLK (time T0)
After 200 clock cycles, RX must be high.
The card must send a response on RX acknowledging the reset between 400 and 40,000 clock cycles after T0.
Figure 22. Internal-reset card reset sequence
Table 22. SIM timing specification—High Drive strength
Num
Description
Symbol
Min
Max
Unit
1
SIM clock frequency (SIM_CLK)1
1 50% duty cycle clock
Sfreq
0.01
5 (Some new cards
may reach 10)
MHz
2
SIM_CLK rise time 2
2 With C = 50pF
Srise
–20
ns
3
SIM_CLK fall time 3
3 With C = 50pF
Sfall
–20
ns
4
SIM input transition time (RX, SIM_PD)
Strans
–25
ns
SIM_CLK
Srise
Sfall
1/Sfreq
SIM_VEN
SIM_CLK
SIM_RX
2
T0
1
Response
2
1
< 200 clock cycles
< 40,000 clock cycles
400 clock cycles <
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