參數(shù)資料
型號(hào): MCF5407FT162
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 162 MHz, RISC PROCESSOR, PQFP208
封裝: 28 X 28 MM, 0.50 MM PITCH, PLASTIC, FQFP-208
文件頁(yè)數(shù): 32/35頁(yè)
文件大?。?/td> 441K
代理商: MCF5407FT162
6
MCF5407 Integrated ColdFire Microprocessor Product Brief
MOTOROLA
ColdFire Module Description
16-bit general-purpose I/O interface
IEEE 1149.1 test (JTAG) module
System debug support
— Real-time trace for determining dynamic execution path while in emulator mode
— Background debug mode (BDM) for debug features while halted
— Real-time debug support, including 13 user-visible hardware breakpoint registers
— Supports servicing of critical, real-time interrupt requests while the BDM is in emulator mode
— Supports comprehensive emulator functions through trace and breakpoint logic
On-chip PLL
— Accepts various clock input (CLKIN) frequencies between 25 and 54 MHz
— Supports core frequencies between 100 and 162 MHz
— Supports low-power mode
Product offerings
— 316 Dhrystone MIPS at 220 MHz
— 233 Dhrystone MIPS at 162 MHz
— Implemented in 0.22 , quad-layer-metal process technology with 1.8-V operation (3.3-V
compliant I/O pads)
— 208-pin plastic QFP package
— 0 to 70° C operating temperature at 162 and 220 MHz
— -40 to 85
° C operating temperature at 162 MHz
1.2.1
Process
The MCF5407 is manufactured in a 0.22- CMOS process with quad-layer-metal routing technology. This
process combines the high performance and low power needed for embedded system applications. Inputs
are 3.3-V tolerant; outputs are CMOS or open-drain CMOS with outputs operating from VDD + 0.5 V to
GND - 0.5 V, with guaranteed TTL-level specifications.
1.3
ColdFire Module Description
The following sections provide overviews of the various modules incorporated in the MCF5407.
1.3.1
ColdFire Core
The Version 4 ColdFire core consists of two, independent and decoupled pipelines to maximize
performance—the instruction fetch pipeline (IFP) and the operand execution pipeline (OEP).
1.3.1.1
Instruction Fetch Pipeline (IFP)
The four-stage instruction fetch pipeline (IFP) is designed to prefetch instructions for the operand execution
pipeline (OEP). Because the fetch and execution pipelines are decoupled by a ten-instruction FIFO buffer,
the fetch mechanism can prefetch instructions in advance of their use by the OEP, thereby minimizing the
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