參數(shù)資料
型號(hào)： MCF5407CFT162
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 162 MHz, RISC PROCESSOR, PQFP208
封裝： 28 X 28 MM, 0.50 MM PITCH, PLASTIC, FQFP-208
文件頁(yè)數(shù)： 6/35頁(yè)
文件大?。?/td> 441K
代理商： MCF5407CFT162
14
MCF5407 Integrated ColdFire Microprocessor Product Brief
MOTOROLA
Programming Model, Addressing Modes, and Instruction Set
1.4.2
User Registers
The user programming model, shown in Figure 4, is summarized in Table 1.
1.4.3
Supervisor Registers
Table 2 summarizes the MCF5407 supervisor-level registers.
Table 1. User-Level Registers
Register
Description
Data registers
(D0–D7)
These 32-bit registers are for bit, byte, word, and longword operands. They can also be used as index
registers.
Address registers
(A0–A7)
These 32-bit registers serve as software stack pointers, index registers, or base address registers. The
base address registers can be used for word and longword operations. A7 functions as a hardware
stack pointer during stacking for subroutine calls and exception handling.
Program counter
(PC)
Contains the address of the instruction currently being executed by the MCF5407 processor.
Condition code
register (CCR)
The CCR is the lower byte of the SR. It contains indicator flags that reflect the result of a previous
operation and are used for conditional instruction execution.
MAC status
register (MACSR)
Defines the operating configuration of the MAC unit and contains indicator flags from the results of MAC
instructions.
Accumulator
(RACC)
General-purpose register used to accumulate the results of MAC operations.
Mask register
(RMASK)
General-purpose register provides an optional address mask for MAC instructions that fetch operands
from memory. It is useful in the implementation of circular queues in operand memory.
Table 2. Supervisor-Level Registers
Register
Description
Status register (SR)
The upper byte of the SR provides interrupt information in addition to a variety of mode indicators
signaling the operating state of the ColdFire processor. The lower byte of the SR is the CCR, as
shown in Figure 4.
Vector base register
(VBR)
Defines the upper 12 bits of the base address of the exception vector table used during exception
processing. The low-order 20 bits are forced to zero, locating the vector table on 0-modulo-1 Mbyte
address.
Cache configuration
register (CACR)
Defines the operating modes of the Version 4 cache memories. Control fields configuring the
instruction, data and branch cache are provided by this register, along with the default attributes for
the 4-Gbyte address space.
Access control
registers (ACR0/1,
ACR2/3)
Define address ranges and attributes associated with various memory regions within the 4-Gbyte
address space. Each ACR defines the location of a given memory region and assigns attributes
such as write-protection and cache mode (copyback, write-through, cacheability). ACR0 and ACR1
support data memory; ACR2 and ACR3 support instruction memory. Additionally, CACR fields
assign default attributes to the instruction and data memory spaces.
RAM base address
registers (RAMBAR0,
RAMBAR1)
Provide the logical base address for the two 2-Kbyte SRAM modules and define attributes and
access types allowed for the corresponding SRAM.
Module base address
register (MBAR)
Defines the logical base address for the memory-mapped space containing the control registers for
the on-chip peripherals.
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