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MOTOROLA
MCF5407 Integrated ColdFire Microprocessor Product Brief
3
MCF5407 Features
Although the MCF5407 offers obvious performance upgrade advantages, its rich memory and peripheral
integration at inexpensive prices should not be overlooked. Features common to many embedded
applications, such as DMAs, various DRAM controller interfaces, and on-chip memories, are integrated in
a cost-effective manner using aggressive process technologies.
The MCF5407 extends the legacy of Motorola’s 68K family by providing a compatible path for 68K and
ColdFire customers in which development tools and customer code are quickly leveraged. In fact, customers
moving from 68K to ColdFire can use code translation and emulation tools that facilitate modifying 68K
assembly code to the ColdFire architecture. The package, pinout, and integration mix of the MCF5407
create an especially simple upgrade for current MCF5307 designs with over triple the system performance.
The revolutionary ColdFire microprocessor architecture provides new levels of price and performance to
cost-sensitive markets. Based on the concept of variable-length RISC technology, the ColdFire family
combines the architectural simplicity of conventional 32-bit RISC with a memory-saving, variable-length
instruction set. In defining the ColdFire architecture for embedded processing applications, a 68K-code
compatible core was created that combines the performance advantages of a RISC architecture with the
optimum code density of a streamlined, variable-length M68000 instruction set.
By using a variable-length instruction set architecture, embedded system designers using ColdFire RISC
processors enjoy significant advantages over conventional fixed-length RISC architectures. The denser
binary code for ColdFire processors consumes less memory than many fixed-length instruction set RISC
processors available. This improved code density means more efficient system memory use for a given
application, and allows use of slower, less costly memory to help achieve a target performance level.
The MCF5407 is the first standard product to implement the Version 4 ColdFire microprocessor core. The
V4 microarchitecture implements a number of advanced techniques, including a Harvard memory
architecture, branch cache acceleration logic, and limited superscalar support (dual-instruction issue), which
contribute to the 316 Dhrystone MIPS performance level. Increasing the internal speed of the core also
allows higher performance while providing the system designer with an easy-to-use lower speed system
interface. The processor complex frequency is an integer multiple, 3 to 6 times, of the external bus
frequency. The core clock can be stopped to support a low-power mode in the MCF5407.
Serial communication channels are provided by two programmable full-duplex UARTs, one of which
provides synchronous communications for soft-modem applications, and an I2C interface module. Four
channels of DMA allow for fast data transfer using a programmable burst mode independent of processor
execution. The two 16-bit general-purpose multimode timers provide separate input and output signals. For
system protection, the processor includes a programmable 16-bit software watchdog timer. In addition,
common system functions such as chip selects, interrupt control, bus arbitration, and an IEEE 1149.1 JTAG
module are included.
A sophisticated debug interface supports background-debug mode plus real-time trace and debug with an
expanded set of on-chip breakpoint registers. This interface is present in all ColdFire standard products and
allows common emulator support across the entire family of microprocessors.
1.2
MCF5407 Features
The following list summarizes MCF5407 features:
ColdFire processor core
— Variable-length RISC, clock-multiplied Version 4 microprocessor core
— Implements Revision B of the ColdFire instruction set architecture (ISA), which leverages the
68K programming model