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Memory Map/Register Definition
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
24-7
24.3.2
UART Mode Register 2 (UMR2n)
The UMR2n registers control UART module configuration. UMR2n can be read or written when
the mode register pointer points to it, which occurs after any access to UMR1n. UMR2n accesses
do not update the pointer.
76
54
32
10
R
CM
TXRTS TXCTS
SB
W
Reset
0
00
000
00
Address
IPSBAR + 0x0200 (UART0); IPSBAR + 0x0240 (UART1);
IPSBAR + 0x0280 (UART2)
After UMR1n is read or written, the pointer points to UMR2n.
Figure 24-4. UART Mode Register 2 (UMR2n)
Table 24-4. UMR2n Field Descriptions
Bits
Name
Description
7–6
CM
modes.
00 Normal
01 Automatic echo
10 Local loop-back
11 Remote loop-back
5
TxRTS
Transmitter ready-to-send. Controls negation of UnRTS to automatically terminate a message
transmission. Attempting to program a receiver and transmitter in the same channel for UnRTS
control is not permitted and disables UnRTS control for both.
0 The transmitter has no effect on UnRTS.
1 In applications where the transmitter is disabled after transmission completes, setting this bit
automatically clears UOP[RTS] one bit time after any characters in the channel transmitter
shift and holding registers are completely sent, including the programmed number of stop bits.