
General Purpose I/O Module
MCF5271 Reference Manual, Rev. 2
12-12
Freescale Semiconductor
12.3.1.2 Port Data Direction Registers (PDDR_x)
The PDDRs control the direction of the port x pin drivers when the pins are configured for general
purpose I/O. The PDDR_x registers are each eight bits wide, but not all ports use all eight bits. The
The PDDRs are read/write. At reset, all bits in the PDDRs are cleared. Setting any bit in a PDDR_x
register configures the corresponding port x pin as an output. Clearing any bit in a PDDR_x
register configures the corresponding pin as an input.
76
54
32
10
R
0
PODR_SDRAM
W
Reset
0
01
111
11
Address
IPSBAR + 0x10_0006 (PODR_SDRAM)
Figure 12-6. Port SDRAM Output Data Register (PODR_SDRAM)
76
54
32
10
R
0
00
000
PODR_UARTH
W
Reset
0
00
000
11
Address
IPSBAR + 0x10_0008 (PODR_UARTH)
Figure 12-7. Port UARTH Output Data Register (PODR_UARTH)
76
54
32
10
R
0
PODR_QSPI
W
Reset
0
00
111
11
Address
IPSBAR + 0x10_000A (PODR_QSPI)
Figure 12-8. Port QSPI Output Data Register (PODR_QSPI)
Table 12-4. PODR_x Field Descriptions
Name
Description
—
Reserved, should be cleared.
PODR_x
Port x output data bits.
0 Drives 0 when the port x pin is general purpose output
1 Drives 1 when the port x pin is general purpose output
Note: See above figures for bit field positions.