參數(shù)資料
型號(hào): MCF5249LPV120
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 120 MHz, RISC PROCESSOR, PQFP144
封裝: 20 X 20 X 1.4 MM, 0.50 MM PITCH, LQFP-144
文件頁數(shù): 84/446頁
文件大小: 5856K
代理商: MCF5249LPV120
11-4
MCF5249UM
MOTOROLA
General-Purpose Timer Registers
11.5.1
TIMER MODE REGISTERS (TMR0, TMR1)
The TMR is a 16-bit memory-mapped register. This register programs the various timer modes and is
cleared by reset.
Table 11-2
Timer Mode Register (TMRn)
BITS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIELD
PRESCALER VALUE (PS7 - PS0)
CE1 - CE0 OM
ORI FRR
CLK1 -
CLK0
RESET
0
0000
0
R/W
READ/WRITE SUPERVISOR OR USER MODE
ADDR
MBAR+$140, MBAR+$180
Table 11-3 Timer Mode Bit Descriptions
BIT NAME
DESCRIPTION
PS7–PS0
The Prescaler Value is programmed to divide the clock input by values from 1 to
256. The value 00000000 divides the clock by 1; the value 11111111 divides the
clock by 256.
Prescalar value = $[PS7 - PS0] + 1
CE1–CE0
Capture Edge and Enable Interrupt
11 = Capture on any edge and enable interrupt on capture event
10 = Capture on falling edge only and enable interrupt on capture event
01 = Capture on rising edge only and enable interrupt on capture event
00 = Disable interrupt on capture event
OM
Output Mode
1 = Toggle output
0 = Active-low pulse for one system clock cycle (14.28 ns at 70 MHz)
ORI
Output Reference Interrupt Enable
1 = Enable interrupt upon reaching the reference value
0 = Disable interrupt for reference reached (does not affect interrupt on capture
function)
Note:
If ORI is set when the REF event is asserted in the Timer Event Register (TER), an
immediate interrupt occurs. If ORI is cleared while an interrupt is asserted, the
interrupt negates.
FRR
Free Run/Restart
1 = Restart: Timer count is reset immediately after reaching the reference value
0 = Free run: Timer count continues to increment after reaching the reference value
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