
19-6
MCF5249UM
MOTOROLA
Background-Debug Mode (BDM)
19.2.1.6
Begin Execution of RTE Instruction (PST = $7)
The unique encoding is generated whenever the return-from-exception (RTE) instruction is executed.
19.2.1.7
Begin Data Transfer (PST = $8–$B)
These encodings serve as markers to indicate the number of bytes to be displayed on the DDATA port on
subsequent clock cycles. This encoding is driven onto the PST port one processor cycle before the actual
data is displayed on DDATA. When PST outputs a $8/$9/$A/$B marker value, the DDATA port outputs
1/2/3/4 bytes of captured data respectively on consecutive processor cycles.
19.2.1.8
Exception Processing (PST = $C)
This encoding is displayed during normal exception processing. Exceptions which enter emulation mode
(debug interrupt, or optionally trace) generate a different encoding. Because this encoding defines a
multicycle mode, the PST outputs are driven with this value until exception processing is completed.
19.2.1.9
Emulator Mode Exception Processing (PST = $D)
This encoding is displayed during emulation mode (debug interrupt, or optionally trace). Because this
encoding defines a multicycle mode, the PST outputs are driven with this value until exception processing
is completed.
19.2.1.10
Processor Stopped (PST = $E)
This encoding is generated as a result of the STOP instruction. The ColdFire processor remains in the
stopped state until an interrupt occurs. Because this encoding defines a multicycle mode, the PST outputs
are driven with this value until the stopped mode is exited.
19.2.1.11
Processor Halted (PST = $F)
Because this encoding defines a multicycle mode, the PST outputs are driven with this value until the
processor is restarted, or reset.
19.3
BACKGROUND-DEBUG MODE (BDM)
Background debug mode (BDM) implements a low-level system debugger in the microprocessor
hardware. Communication with the development system is handled through a dedicated, high-speed,
full-duplex serial command interface. The BDM features are as follows:
ColdFire implements the BDM controller in a dedicated hardware module. Although some BDM
operations do require the CPU to be halted (For example, CPU register accesses), other BDM
commands such as memory accesses can be executed while the processor is running.
The read/write control register commands, RCREG and WCREG use the register coding scheme
from the MOVEC instruction.
The read/write debug module register commands, RDMREG and WDMREG support debug module
register accesses.
Illegal command responses can be returned using the FILL and DUMP commands, if not immediately
preceded by certain, specific BDM commands.
For any command performing a byte-sized memory read operation, the upper 8 bits of the response
data are undefined. The referenced data is returned in the lower 8 bits of the response.
The debug module forces alignment for memory-referencing operations: long accesses are forced to
a 0-modulo-4 address; word accesses are forced to a 0-modulo-2 address. An address error
response is never returned.