參數(shù)資料
型號： MCF52235
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： ColdFire Microcontroller
中文描述： ColdFire微控制器
文件頁數(shù)： 26/50頁
文件大?。?/td> 656K
代理商： MCF52235
MCF52235 ColdFire Microcontroller, Rev. 3
MCF52235 Family Configurations
Freescale Semiconductor
26
Test Data Output
TDO
Serial output for test instructions and data. TDO is tri-stateable and is
actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
O
Development Serial
Clock
DSCLK
Development Serial Clock. Internally synchronized input. (The logic
level on DSCLK is validated if it has the same value on two
consecutive rising bus clock edges.) Clocks the serial communication
port to the debug module during packet transfers. Maximum frequency
is PSTCLK/5. At the synchronized rising edge of DSCLK, the data
input on DSI is sampled and DSO changes state.
I
Breakpoint
BKPT
Breakpoint. Input used to request a manual breakpoint. Assertion of
BKPT puts the processor into a halted state after the current
instruction completes. Halt status is reflected on processor status
signals (PST[3:0]) as the value 0xF. If CSR[BKD] is set (disabling
normal BKPT functionality), asserting BKPT generates a debug
interrupt exception in the processor.
I
Development Serial
Input
DSI
Development Serial Input. Internally synchronized input that provides
data input for the serial communication port to the debug module after
the DSCLK has been seen as high (logic 1).
I
Development Serial
Output
DSO
Development Serial Output. Provides serial output communication for
debug module responses. DSO is registered internally. The output is
delayed from the validation of DSCLK high.
O
Debug Data
DDATA[3:0]
Display captured processor data and breakpoint status. The CLKOUT
signal can be used by the development system to know when to
sample DDATA[3:0].
O
Processor Status Clock
PSTCLK
Processor Status Clock. Delayed version of the processor clock. Its
rising edge appears in the center of valid PST and DDATA output.
PSTCLK indicates when the development system should sample PST
and DDATA values.
If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, PST,
and DDATA outputs from toggling without disabling triggers.
Non-quiescent operation can be re-enabled by clearing CSR[PCD],
although the external development systems must resynchronize with
the PST and DDATA outputs.
PSTCLK starts clocking only when the first non-zero PST value (0xC,
0xD, or 0xF) occurs during system reset exception processing.
O
Processor Status
Outputs
PST[3:0]
Indicate core status. Debug mode timing is synchronous with the
processor clock; status is unrelated to the current bus transfer. The
CLKOUT signal can be used by the development system to know
when to sample PST[3:0].
O
All Processor Status
Outputs
ALLPST
Logical AND of PST[3:0]
O
Table 16. Debug Support Signals (continued)
Signal Name
Abbreviation
Function
I/O
相關(guān)PDF資料
PDF描述
MCF5232CAB80 Integrated Microprocessor Hardware Specification
MCF5232 Integrated Microprocessor Hardware Specification
MCF5249 CodeWarrior Development Studio for ColdFire㈢ Architectures
MCF5251_07 ColdFire㈢ Microprocessor Data Sheet
MCF5251 ColdFire Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCF52235_06 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ColdFire㈢ Microcontroller
MCF52235_07 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller
MCF52235_10 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF52235 ColdFire Microcontroller Data Sheet
MCF52235CAL60 功能描述:32位微控制器 - MCU KIRIN2E EPP RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT
MCF52235CAL60A 制造商:Freescale Semiconductor 功能描述:KIRIN2E EPP - REV A - Bulk
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