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參數(shù)資料
| 型號(hào)： | MCF52223_07 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | ColdFire Microcontroller |
| 中文描述： | ColdFire微控制器 |
| 文件頁數(shù)： | 24/56頁 |
| 文件大小： | 962K |
| 代理商： | MCF52223_07 |
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MCF52223 ColdFire Microcontroller, Rev. 2
MCF52223 Family Configurations
Freescale Semiconductor
24
1.13
General Purpose Timer Signals
Table 13
describes the general purpose timer signals.
1.14
Pulse Width Modulator Signals
Table 14
describes the PWM signals.
1.15
Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and the BDM logic.
Table 13. GPT Signals
Signal Name
Abbreviation
Function
I/O
General Purpose Timer
Input/Output
GPT[3:0]
Inputs to or outputs from the general purpose timer module.
I/O
Table 14. PWM Signals
Signal Name
Abbreviation
Function
I/O
PWM Output Channels
PWM[7:0]
Pulse width modulated output for PWM channels.
O
Table 15. Debug Support Signals
Signal Name
Abbreviation
Function
I/O
JTAG Enable
JTAG_EN
Select between debug module and JTAG signals at reset.
I
Test Reset
TRST
This active-low signal is used to initialize the JTAG logic
asynchronously.
I
Test Clock
TCLK
Used to synchronize the JTAG logic.
I
Test Mode Select
TMS
Used to sequence the JTAG state machine. TMS is sampled on the
rising edge of TCLK.
I
Test Data Input
TDI
Serial input for test instructions and data. TDI is sampled on the rising
edge of TCLK.
I
Test Data Output
TDO
Serial output for test instructions and data. TDO is tri-stateable and is
actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
O
Development Serial
Clock
DSCLK
Development Serial Clock - Internally synchronized input. (The logic
level on DSCLK is validated if it has the same value on two
consecutive rising bus clock edges.) Clocks the serial communication
port to the debug module during packet transfers. Maximum frequency
is PSTCLK/5. At the synchronized rising edge of DSCLK, the data
input on DSI is sampled and DSO changes state.
I
Breakpoint
BKPT
Breakpoint - Input used to request a manual breakpoint. Assertion of
BKPT puts the processor into a halted state after the current
instruction completes. Halt status is reflected on processor
status/debug data signals (PST[3:0] and PSTDDATA[7:0]) as the
value 0xF. If CSR[BKD] is set (disabling normal BKPT functionality),
asserting BKPT generates a debug interrupt exception in the
processor.
I
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| MCF52223CAF66 | 功能描述:32位微控制器 - MCU 32-BIT MCU W/ USB FS OTG RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| MCF52223CAF66 | 制造商:Freescale Semiconductor 功能描述:IC 32BIT MCU MCF52 100-LQFP 制造商:Freescale Semiconductor 功能描述:IC, 32BIT MCU, MCF52, 100-LQFP |
| MCF52223CAF80 | 功能描述:32位微控制器 - MCU 32-BIT MCU W/ USB FS OTG RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| MCF52223CVM66 | 功能描述:32位微控制器 - MCU 32-BIT MCU W/ USB FS OTG RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| MCF52223CVM66J | 功能描述:32位微控制器 - MCU 32-BIT MCU W/USB FLS RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
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