參數(shù)資料
型號： MCF51QH128VLH
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： FLASH, 50 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, LQFP-64
文件頁數(shù)： 7/72頁
文件大?。?/td> 1031K
代理商： MCF51QH128VLH
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLLS1
Very low-leakage stop mode 1 current at 3.0 V
@ –40 to 25 °C
@ 70 °C
@ 105 °C
—
1.3
TBD
μA
IDD_OSC
Average current for OSC enabled with 32 kHz
crystal at 3.0 V
@ –40 to 25 °C
@ 70 °C
@ 105 °C
—
0.7
TBD
—
μA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks disabled.
3. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks enabled, but
peripherals are not in active operation.
4. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks enabled, and
peripherals are in active operation.
5. 25 MHz core and system clocks, and 12.5 MHz bus clock. MCG configured for FEI mode.
6. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode.
7. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for BLPE mode. All peripheral clocks disabled.
Code executing from flash memory.
8. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for BLPE mode. All peripheral clocks enabled, but
peripherals are not in active operation. Code executing from flash memory.
9. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for BLPE mode. All peripheral clocks disabled.
10. OSC clocks disabled.
11. All pads disabled.
12. Data reflects devices with 32 KB of RAM. For devices with 16 KB of RAM, power consumption is reduced by 500 nA. For
devices with 8 KB of RAM, power consumption is reduced by 750 nA.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
All peripheral clocks disabled except FTFL
LVD disabled, USB voltage regulator disabled
No GPIOs toggled
Code execution from flash memory
DIAGRAM TBD
Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled
The following data was measured under these conditions:
MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
All peripheral clocks enabled, but peripherals are not in active operation
Nonswitching electrical specifications
MCF51JF128 Advance Information Data Sheet, Rev. 3, 08/2011.
Freescale Semiconductor, Inc.
Preliminary
15
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