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參數(shù)資料
| 型號： | MCF51QH128VLH |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FLASH, 50 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, LQFP-64 |
| 文件頁數(shù)： | 46/72頁 |
| 文件大小： | 1031K |
| 代理商： | MCF51QH128VLH |
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6.8.5 I2S/SAI Switching Specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
All timing shown is also with respect to input signal transitions of 3 ns and a 50 pF
maximum load.
Table 36. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time1
40
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK cycle time (output)1
I2S_RX_BCLK cycle time (output)1
80
160
—
ns
S4
I2S_TX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
25
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
S11
I2S_TX_FS input assertion to I2S_TXD output valid2
—
21
ns
1. This parameter is limited in VLPx modes.
2. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Communication interfaces
MCF51JF128 Advance Information Data Sheet, Rev. 3, 08/2011.
50
Preliminary
Freescale Semiconductor, Inc.
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