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| 型號(hào)： | MCF51QH128VLF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FLASH, 50 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, LQFP-48 |
| 文件頁(yè)數(shù)： | 29/72頁(yè) |
| 文件大小： | 1031K |
| 代理商： | MCF51QH128VLF |
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Analog
6.6.1 ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications.
6.6.1.1 12-bit ADC operating conditions
Table 23. 12-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Max.
Unit
Notes
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDD-
VDDA)
-100
0
+100
mV
ΔVSSA
Ground voltage
Delta to VSS (VSS-
VSSA)
-100
0
+100
mV
VREFH
ADC reference
voltage high
1.13
VDDA
V
VREFL
Reference
voltage low
VSSA
V
VADIN
Input voltage
VREFL
—
VREFH
V
CADIN
Input
capacitance
8/10/12 bit
modes
—
4
5
pF
RADIN
Input resistance
—
2
5
kΩ
RAS
Analog source
resistance
12 bit modes
fADCK < 4MHz
—
5
kΩ
fADCK
ADC conversion
clock frequency
≤ 12 bit modes
1.0
—
18.0
MHz
Crate
ADC conversion
rate
≤ 12 bit modes
No ADC hardware
averaging
Continuous
conversions enabled,
subsequent conversion
time
20.000
—
818.330
Ksps
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the
best results. The results in this datasheet were derived from a system which has <8 Ω analog source resistance. The RAS/
CAS time constant should be kept to <1ns.
4. To use the maximum ADC conversion clock frequency, the ADHSC bit should be set and the ADLPC bit should be clear.
6.6
Analog
MCF51JF128 Advance Information Data Sheet, Rev. 3, 08/2011.
Freescale Semiconductor, Inc.
Preliminary
35
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