參數(shù)資料
型號(hào): MCF51AG128VLK
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, PQFP80
封裝: 14 X 14 MM, 1.40 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù): 22/50頁(yè)
文件大?。?/td> 1630K
代理商: MCF51AG128VLK
Preliminary Electrical Characteristics
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
29
10
D FLL acquisition time 3
tfll_acquire
——
1
ms
11
D Long term Jitter of DCO output clock (averaged over
2ms interval) 4
CJitter
—0.02
0.2
%fdco
12
D Loss of external clock minimum freq. (RANGE = 0)
ext. clock freq: above (3/5)fint, never reset
ext. clock freq: between (2/5)fint and (3/5)fint, maybe
reset (phase dependency)
ext. clock freq: below (2/5)fint, always reset
floc_low
(3/5) x fint
kHz
13
D Loss of external clock minimum freq. (RANGE = 1)
ext. clock freq: above (16/5)fint, never reset
ext. clock freq: between (15/5)fint and (16/5)fint,
maybe reset (phase dependency)
ext. clock freq: below (15/5)fint, always reset
floc_high
(16/5) x fint
kHz
1 Data in Typical column was characterized at 3.0 V, 25
°C or is typical recommended value
2 The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the
reference, this specification assumes it is already running.
4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
BUS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry by VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for
a given interval.
Table 15. ICS Frequency Specifications (continued)(Temperature Range = –40 to 105
°C Ambient)
Num C
Rating
Symbol
Min
Typical1
Max
Unit
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