參數(shù)資料
型號: MCF51AC256AVFUE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 50.33 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, LEAD FREE, QFP-64
文件頁數(shù): 24/46頁
文件大小: 1036K
代理商: MCF51AC256AVFUE
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.4
Electrical Characteristics
Freescale Semiconductor
30
2.11.1
Control Timing
Figure 9. Reset Timing
Figure 10. IRQ/KBIPx Timing
Table 17. Control Timing
Num
C
Parameter
Symbol
Min
Typical1
1 Typical values are based on characterization data at V
DD = 5.0 V, 25 °C unless otherwise stated.
Max
Unit
1
D
Bus frequency (tcyc = 1/fBus)fBus
dc
24
MHz
2
D
Internal low-power oscillator period
tLPO
800
1500
μs
3D
External reset pulse width2
(tcyc = 1/fSelf_reset)
2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
textrst
100
ns
4
D
Reset low drive
trstdrv
66
× t
cyc
——
ns
5
D
Active background debug mode latch setup time
tMSSU
500
ns
6
D
Active background debug mode latch hold time
tMSH
100
ns
7D
IRQ pulse width
Asynchronous path2
Synchronous path3
3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
tILIH, tIHIL
100
1.5
× t
cyc
——
ns
8D
KBIPx pulse width
Asynchronous path2
Synchronous path3
tILIH, tIHIL
100
1.5
× t
cyc
——
ns
9D
Port rise and fall time (load = 50 pF)4
Slew rate control disabled (PTxSE = 0), Low Drive
Slew rate control enabled (PTxSE = 1), Low Drive
Slew rate control disabled (PTxSE = 0), Low Drive
Slew rate control enabled (PTxSE = 1), Low Drive
4 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40 °C to 105 °C.
tRise, tFall
11
35
40
75
—ns
textrst
RESET PIN
tIHIL
IRQ/KBIPx
tILIH
IRQ/KBIPx
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