參數(shù)資料
型號： MC9SDG128BMPVR2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP112
封裝： 20 X 20 MM, 1.40 MM HEIGHT, 0.65 MM PITCH, LQFP-112
文件頁數(shù)： 26/128頁
文件大?。?/td> 2002K
代理商： MC9SDG128BMPVR2
MC9S12DT128B Device User Guide — V01.09
119
Table A-20 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
P Frequency of operation (E-clock)
fo
0
25.0
MHz
2
P Cycle time
tcyc
40
ns
3
D Pulse width, E low
PWEL
19
ns
4D Pulse width, E high1
PWEH
19
ns
5
D Address delay time
tAD
8ns
6D Address valid time to E rise (PWEL–tAD)tAV
11
ns
7
D Muxed address hold time
tMAH
2ns
8
D Address hold to data valid
tAHDS
7ns
9
D Data hold to address
tDHA
2ns
10
D Read data setup time
tDSR
13
ns
11
D Read data hold time
tDHR
0ns
12
D Write data delay time
tDDW
7ns
13
D Write data hold time
tDHW
2ns
14
D Write data setup time(1) (PWEH–tDDW)
tDSW
12
ns
15
D Address access time(1) (tcyc–tAD–tDSR)
tACCA
19
ns
16
D E high access time(1) (PWEH–tDSR)
tACCE
6ns
17
D Non-multiplexed address delay time
tNAD
6ns
18
D Non-muxed address valid to E rise (PWEL–tNAD)tNAV
15
ns
19
D Non-multiplexed address hold time
tNAH
2ns
20
D Chip select delay time
tCSD
16
ns
21
D Chip select access time(1) (tcyc–tCSD–tDSR)
tACCS
11
ns
22
D Chip select hold time
tCSH
2ns
23
D Chip select negated time
tCSN
8ns
24
D Read/write delay time
tRWD
7ns
25
D Read/write valid time to E rise (PWEL–tRWD)tRWV
14
ns
26
D Read/write hold time
tRWH
2ns
27
D Low strobe delay time
tLSD
7ns
28
D Low strobe valid time to E rise (PWEL–tLSD)tLSV
14
ns
29
D Low strobe hold time
tLSH
2ns
30
D NOACC strobe delay time
tNOD
7ns
31
D NOACC valid time to E rise (PWEL–tNOD)tNOV
14
ns
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