
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
441
10.3.2.17 MSCAN Identier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identier acceptance and identier mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see
Section 10.3.3.1,For extended identiers, all four acceptance and mask registers are applied. For standard identiers, only
the rst two (CANIDAR0/1, CANIDMR0/1) are applied.
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Module Base + 0x0010 (CANIDAR0)
0x0011 (CANIDAR1)
0x0012 (CANIDAR2)
0x0013 (CANIDAR3)
76543210
R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
W
Reset
00000000
76543210
R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
W
Reset
00000000
76543210
R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
W
Reset
00000000
76543210
R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
W
Reset
00000000
Figure 10-20. MSCAN Identier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3