
Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
MC9S12E256 Data Sheet, Rev. 1.10
378
Freescale Semiconductor
Figure 11-71. Half-Cycle Center-Aligned Modulus Loading
Figure 11-72. Edge-Aligned PWM Value Loading
Figure 11-73. Untitled Figure
11.4.7.4
Initialization
Initialize all registers and set the LDOK bit before setting the PWMEN bit. With LDOK set, setting
PWMEN for the rst time after reset, immediately loads the PWM generator thereby setting the PWMRF
ag. PWMRF generates a CPU interrupt request if the PWMRIE bit is set. In complementary channel
UP/DOWN
PWM
HALF = 1, LDFQ[3:0] = 00 = RELOAD EVERY HALF-CYCLE
LDOK = 1
MODULUS = 2
PWM VALUE = 1
PWMRF = 1
0
3
1
0
4
1
0
2
1
COUNTER
0
2
1
4
1
4
1
UP ONLY
PWM
LDFQ[3:0] = 00 = RELOAD EVERY CYCLE
COUNTER
LDOK = 1
MODULUS = 3
PWM VALUE = 1
PWMRF = 1
0
3
2
1
3
2
1
0
3
1
0
3
1
UP ONLY
PWM
LDFQ[3:0] = 00 = RELOAD EVERY CYCLE
LDOK = 1
MODULUS = 3
PWM VALUE = 2
PWMRF = 1
COUNTER
1
4
2
1
2
1
0
1
2
1