Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1)
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor
25
1.2
Device Memory Map
Table 1-1 shows the device register map of the MC9S12E256 after reset.
Figure 1-2 illustrates the device
memory map with Flash and RAM.
Table 1-1. Device Register Map Overview
Address
Module
Size
0x0000–0x0017
CORE (Ports A, B, E, Modes, Inits, Test)
24
0x0018
Reserved
1
0x0019
Voltage Regulator (VREG)
1
0x001A–0x001B
Device ID register (PARTID)
2
0x001C–0x001F
CORE (MEMSIZ, IRQ, HPRIO)
4
0x0020–0x002F
CORE (DBG)
16
0x0030–0x0033
CORE (PPAGE, Port K)
4
0x0034–0x003F
Clock and Reset Generator (PLL, RTI, COP)
12
0x0040–0x006F
Standard Timer 16-bit 4 channels (TIM0)
48
0x0070–0x007F
Reserved
16
0x0080–0x00AF
Analog to Digital Converter 10-bit 16 channels (ATD)
48
0x00B0–0x00C7
Reserved
24
0x00C8–0x00CF
Serial Communications Interface 0 (SCI0)
8
0x00D0–0x00D7
Serial Communications Interface 1 (SCI1)
8
0x00D8–0x00DF
Serial Peripheral Interface (SPI)
8
0x00E0–0x00E7
Inter IC Bus
8
0x00E8–0x00EF
Serial Communications Interface 2 (SCI2)
8
0x00F0–0x00F3
Digital to Analog Converter 8-bit 1-channel (DAC0)
4
0x00F4–0x00F7
Digital to Analog Converter 8-bit 1-channel (DAC1)
4
0x00F8–0x00FF
Reserved
8
0x0100- 0x010F
Flash Control Register
16
0x0110–0x013F
Reserved
48
0x0140–0x016F
Standard Timer 16-bit 4 channels (TIM1)
48
0x0170–0x017F
Reserved
16
0x0180–0x01AF
Standard Timer 16-bit 4 channels (TIM2)
48
0x01B0–0x01DF
Reserved
48
0x01E0–0x01FF
Pulse Width Modulator 8-bit 6 channels (PWM)
32
0x0200–0x023F
Pulse Width Modulator with Fault 15-bit 6 channels (PMF)
64
0x0240–0x027F
Port Integration Module (PIM)
64
0x0280–0x03FF
Reserved
384
