參數(shù)資料
型號: MC9S12DJ128B
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Device User Guide V01.09
中文描述: 設(shè)備的用戶手冊V01.09
文件頁數(shù): 79/128頁
文件大小: 729K
代理商: MC9S12DJ128B
Section 6 HCS12 Core Block Description
Consult the HCS12 Core User Guide for information about the HCS12 core modules, i.e. central
processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed
external bus interface (MEBI), breakpoint module (BKP) and background debug mode module (BDM).
6.1 Device-specific information
When the BDM section of S12 Core User Guide refers to
alternate clock
this is equivalent to
oscillator
clock
.
Section 7 Clock and Reset Generator (CRG) Block
Description
Consult the CRG Block User Guide for information about the Clock and Reset Generator module.
7.1 Device-specific information
7.1.1 XCLKS
The XCLKS input signal is active low (see
2.3.12 PE7 / NOACC / XCLKS — Port E I/O Pin 7
).
Section 8 Enhanced Capture Timer (ECT) Block
Description
Consult the ECT_16B8C Block User Guide for information about the Enhanced Capture Timer
module.When the ECT_16B8C Block User Guide refers to
freeze mode
this is equivalent to
active BDM
mode
.
Section 9 Analog to Digital Converter (ATD) Block
Description
There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12DT128B.
Consult the ATD_10B8C Block User Guide for information about each Analog to Digital Converter
module. When the ATD_10B8C Block User Guide refers to
freeze mode
this is equivalent to
active BDM
mode
.
Section 10 Inter-IC Bus (IIC) Block Description
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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