
Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
99
BRCLR n,opr8a,rel
Branch if Bit n in Memory
Clear
Branch if (Mn) = 0
–––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
5
BRN rel
Branch Never
Uses 3 Bus Cycles
–––––– REL
21 rr
3
BRSET n,opr8a,rel
Branch if Bit n in Memory
Set
Branch if (Mn) = 1
–––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
5
BSET n,opr8a
Set Bit n in Memory
Mn
← 1
–––––– DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
5
BSR rel
Branch to Subroutine
PC
← (PC) + 0x0002
push (PCL); SP
← (SP) – 0x0001
push (PCH); SP
← (SP) – 0x0001
PC
← (PC) + rel
––––––
REL
AD rr
5
CBEQ opr8a,rel
CBEQA #opr8i,rel
CBEQX #opr8i,rel
CBEQ oprx8,X+,rel
CBEQ ,X+,rel
CBEQ oprx8,SP,rel
Compare and Branch if
Equal
Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
–––––– DIR
IMM
IX1+
IX+
SP1
31
41
51
61
71
9E61
dd rr
ii
rr
ii
rr
ff
rr
ff
rr
5
4
5
6
CLC
Clear Carry Bit
C
← 0
–––––0 INH
98
1
CLI
Clear Interrupt Mask Bit
I
← 0
––0––– INH
9A
1
CLR opr8a
CLRA
CLRX
CLRH
CLR oprx8,X
CLR ,X
CLR oprx8,SP
Clear
M
← 0x00
A
← 0x00
X
← 0x00
H
← 0x00
M
← 0x00
M
← 0x00
M
← 0x00
0––01– DIR
INH
IX1
IX
SP1
3F
4F
5F
8C
6F
7F
9E6F
dd
ff
5
1
5
4
6
CMP #opr8i
CMP opr8a
CMP opr16a
CMP oprx16,X
CMP oprx8,X
CMP ,X
CMP oprx16,SP
CMP oprx8,SP
Compare Accumulator
with Memory
(A) – (M)
(CCR Updated But Operands Not
Changed)
––
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A1
B1
C1
D1
E1
F1
9ED1
9EE1
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
3
5
4
COM opr8a
COMA
COMX
COM oprx8,X
COM ,X
COM oprx8,SP
Complement
(One’s Complement)
M
← (M)= 0xFF – (M)
A
← (A) = 0xFF – (A)
X
← (X) = 0xFF – (X)
M
← (M) = 0xFF – (M)
M
← (M) = 0xFF – (M)
M
← (M) = 0xFF – (M)
0––
1 DIR
INH
IX1
IX
SP1
33
43
53
63
73
9E63
dd
ff
5
1
5
4
6
CPHX opr16a
CPHX #opr16i
CPHX opr8a
CPHX oprx8,SP
Compare Index Register
(H:X) with Memory
(H:X) – (M:M + 0x0001)
(CCR Updated But Operands Not
Changed)
––
EXT
IMM
DIR
SP1
3E
65
75
9EF3
hh ll
jj
kk
dd
ff
6
3
5
6
Table 7-2. HCS08 Instruction Set Summary (Sheet 3 of 7)
Source
Form
Operation
Description
Effect
on CCR
Ad
dress
Mode
Opcode
Operand
Bus
Cyc
les
1
VH I N Z C