參數(shù)資料
型號(hào): MC9RS08KA1CDBR
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 7/136頁(yè)
文件大?。?/td> 0K
描述: IC CPU RS08 1K FLASH 62RAM 6-DFN
產(chǎn)品培訓(xùn)模塊: USBSpyder08 Discovery Kit
MC9RS08KA8 Microcontroller
標(biāo)準(zhǔn)包裝: 2,500
系列: RS08
核心處理器: RS08
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: LVD,POR,WDT
輸入/輸出數(shù): 2
程序存儲(chǔ)器容量: 1KB(1K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 63 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 6-VDFN 裸露焊盤
包裝: 帶卷 (TR)
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Chapter 12 Development Support
MC9RS08KA2 Series Data Sheet, Rev. 4
104
Freescale Semiconductor
12.4.2
BDC Breakpoint Match Register
This 16-bit register holds the 14-bit address for the hardware breakpoint in the BDC. The BKPTEN and
FTS control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC
commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register.
Breakpoints are normally set while the target MCU is in active background mode before running the user
application program. However, because READ_BKPT and WRITE_BKPT are non-intrusive commands,
they could be executed even while the user program is running. For additional information about setup and
use of the hardware breakpoint logic in the BDC, refer to the RS08 Family Reference Manual.”
5
BKPTEN
BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select)
control bit and BDCBKPT match register are ignored
0 BDC breakpoint disabled.
1 BDC breakpoint enabled.
4
FTS
Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the
BDCBKPT match register
. When FTS = 0, a match between the CPU address bus and the BDCBKPT register
causes the fetched opcode to be tagged
. If this tagged opcode ever reaches the end of the instruction queue,
the CPU enters active background mode rather than executing the tagged opcode
.
0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that
instruction.
1 Breakpoint match forces active background mode at next instruction boundary (address need not be an
opcode).
2
WS
Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function
.
However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active
background mode where all BDC commands work
. Whenever the host forces the target MCU into active
background mode, the host must issue a READ_STATUS command to check that BDMACT = 1 before
attempting other BDC commands
.
0 Target CPU is running user application code or in active background mode (was not in wait or stop mode when
background became active).
1 Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from wait or stop to
active background mode.
1
WSF
Wait or Stop Failure Status — This status bit is set if a memory access command failed due to the target CPU
executing a wait or stop instruction at or about the same time
. The usual recovery strategy is to issue a
BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command
that failed, then return to the user program
. (Typically, the host would restore CPU registers and stack values and
re-execute the wait or stop instruction
.)
0 Memory access did not conflict with a wait or stop instruction.
1 Memory access command failed because the CPU entered wait or stop mode.
Table 12-1. BDCSCR Register Field Descriptions (continued)
Field
Description
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