參數(shù)資料
型號: MC9328MXLCVH15
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: 微處理器
英文描述: i.MX Integrated Portable System Processor
中文描述: i.MX處理器集成的便攜式系統(tǒng)
文件頁數(shù): 92/96頁
文件大?。?/td> 1495K
代理商: MC9328MXLCVH15
MC9328MX1 Advance Information, Rev. 4
92
Freescale Semiconductor
Specifications
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and
setup time, according to:
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore:
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
5
csi_pixclk low time
10.42
ns
6
csi_pixclk frequency
0
48
MHz
Table 43. Non-Gated Clock Mode Parameters (Continued)
Ref No.
Parameter
Minimum
Maximum
Unit
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