參數(shù)資料
型號: MC9328MXLCVH15
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: 微處理器
英文描述: i.MX Integrated Portable System Processor
中文描述: i.MX處理器集成的便攜式系統(tǒng)
文件頁數(shù): 64/96頁
文件大?。?/td> 1495K
代理商: MC9328MXLCVH15
MC9328MX1 Advance Information, Rev. 4
64
Freescale Semiconductor
Specifications
3.15 Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal MMC/SD
module data bus, and internal system FIFO access through a dedicated state machine that monitors the status of
FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/SD module (inner system) and
the application (user programming).
Figure 47. Chip-Select Read Cycle Timing Diagram
Table 29. SDHC Bus Timing Parameter Table
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Min
Max
Min
Max
1
CLK frequency at Data transfer Mode (PP)
1
10/30 cards
1.
2.
3.
C
L
100 pF / 250 pF (10/30 cards)
C
L
250 pF (21 cards)
C
L
25 pF (1 card)
0
25/5
0
25/5
MHz
2
CLK frequency at Identification Mode
2
0
400
0
400
KHz
3a
Clock high time
1
10/30 cards
6/33
10/50
ns
3b
Clock low time
1
10/30 cards
15/75
10/50
ns
4a
Clock fall time
1
10/30 cards
10/50 (5.00)
3
10/50
ns
4b
Clock rise time
1
10/30 cards
14/67 (6.67)
3
10/50
ns
5a
Input hold time
3
10/30 cards
5.7/5.7
5/5
ns
5b
Input setup time
3
10/30 cards
5.7/5.7
5/5
ns
6a
Output hold time
3
10/30 cards
5.7/5.7
5/5
ns
6b
Output setup time
3
10/30 cards
5.7/5.7
5/5
ns
7
Output delay time
3
0
16
0
14
ns
Bus Clock
5b
6b
6a
7
5a
4a
3a
CMD_DAT Input
CMD_DAT Output
4b
3b
Valid Data
Valid Data
Valid Data
Valid Data
1
2
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