參數(shù)資料
型號(hào)： MC9328MXL15
廠(chǎng)商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 150 MHz, MICROPROCESSOR, PBGA256
封裝： 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256
文件頁(yè)數(shù)： 75/84頁(yè)
文件大小： 1492K
代理商： MC9328MXL15
Specifications
MOTOROLA
MC9328MXL Advance Information
77
3.18 CMOS Sensor Interface
The CSI module consists of a control register to configure the interface timing, a control register for
statistic data generation, a status register, interface logic, a 32
× 32 image data receive FIFO, and a 16 × 32
statistic data FIFO. Figure 64 shows the timing diagram when the CMOS sensor output data is configured
for negative edge and the CSI is programmed to received data in positive edge. The parameters for the
timing diagram are listed in Table 29 on page 78.
Figure 64. CSI Signal Timing Diagram
Synchronous Internal Clock Operation (Port B Alternate Function2)
31
SRXD setup before STCK falling
18.81
—
16.5
—
ns
32
SRXD hold after STCK falling
0
—
0—
ns
Synchronous External Clock Operation (Port B Alternate Function2)
33
SRXD setup before STCK falling
1.14
—
1.0
—
ns
34
SRXD hold after STCK falling
0
—
0—
ns
1.
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a
non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync
STFS/SRFS shown in the tables and in the figures.
2.
There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad
261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they
can be viewed both at Port C primary function and Port B alternate function. When SSI signals are
configured as inputs, the SSI module selects the input based on FMCR register bits in the Clock controller
module (CRM). By default, the input are selected from Port C primary function.
3.
bl = bit length; wl = word length.
Table 28. SSI (Port B Alternate Function) Timing Parameter Table (Continued)
Ref No.
Parameter
1.8V ± 0.10V
3.0V ± 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
csi_pixclk
4b
4a
3a
2a
1
csi_hsync/csi_d
3b
2b
csi_vsync
valid_data
5
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