參數(shù)資料
型號: MC9328MX21SCVM
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA289
封裝: 17 X17 MM, 1.45 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-289
文件頁數(shù): 47/88頁
文件大?。?/td> 975K
代理商: MC9328MX21SCVM
Specifications
MC9328MX21S Technical Data, Rev. 1.3
Freescale Semiconductor
51
Figure 41. Read Timing
The precision of the generated clock is very important to get a proper behavior of the one-wire module.
This module is based on a state machine which undertakes actions at defined times.
The most stringent constraint is 0.0645 as a relative time imprecision.
The time relative precision is directly derived from the frequency of the derivative clock (f):
Time relative precision = 1/f -1 = divider/clock (MHz) - 1
The Figure 34 gathers relative time precision for different main clock frequencies.
This shows that the user should take care of the main clock frequency when using the one-wire module. If
the main clock is an exact integer multiple of 1 MHz, then the generated frequency will be exactly 1 MHz.
NOTE:
A main clock frequency below 10 MHz might cause a misbehavior of the module.
Table 33. System Timing Requirements
Times
Values
(Microsec)
Minimum
(Microsec)
Maximum
(microsec)
Absolute
Precision
Relative
Precision
RSTL
511
480
31
0.0645
PST
68
60
75
7
0.1
RSTH
512
480
32
0.0645
LOW0
100
60
120
20
0.2
LOWR
5
1
15
4
0.8
READ_sample
13
15
2
0.15
Table 34. System Clock Requirements
Main Clock Frequency (MHz)
13
16.8
19.44
Clock divide ratio
13
17
19
Generated frequency (MHz)
1
0.9882
1.023
Relative time imprecision
0
0.0117
0.023
60us
one-wire
5us
BUS
Read Timing
Read “0” Slot 117us
Read “1” Slot 117us
13us
5us
13us
One-Wire samples
Set WR1/RD
Auto Clear WR1/RD Set WR1/RD
Auto Clear WR1/R
(set RDST)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX21
Product
Family
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參數(shù)描述
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