參數(shù)資料
型號(hào): MC9328MX21SCVM
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA289
封裝: 17 X17 MM, 1.45 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-289
文件頁(yè)數(shù): 42/88頁(yè)
文件大?。?/td> 975K
代理商: MC9328MX21SCVM
Specifications
MC9328MX21S Technical Data, Rev. 1.3
Freescale Semiconductor
47
11a
(Tx) CK high to STXD high
0.34
0.72
0.34
0.72
ns
11b
(Tx) CK high to STXD low
0.34
0.72
0.34
0.72
ns
12
(Tx) CK high to STXD high impedance
0.34
0.48
0.34
0.48
ns
13
SRXD setup time before (Rx) CK low
21.50
21.50
ns
14
SRXD hold time after (Rx) CK low
0
0
ns
External Clock Operation (SSI2 Ports)
15
(Tx/Rx) CK clock period1
90.91
90.91
ns
16
(Tx/Rx) CK clock high period
36.36
36.36
ns
17
(Tx/Rx) CK clock low period
36.36
36.36
ns
18
(Tx) CK high to FS (bl) high
10.40
17.37
8.67
15.88
ns
19
(Rx) CK high to FS (bl) high
11.00
19.70
9.28
18.21
ns
20
(Tx) CK high to FS (bl) low
10.40
17.37
8.67
15.88
ns
21
(Rx) CK high to FS (bl) low
11.00
19.70
9.28
18.21
ns
22
(Tx) CK high to FS (wl) high
10.40
17.37
8.67
15.88
ns
23
(Rx) CK high to FS (wl) high
11.00
19.70
9.28
18.21
ns
24
(Tx) CK high to FS (wl) low
10.40
17.37
8.67
15.88
ns
25
(Rx) CK high to FS (wl) low
11.00
19.70
9.28
18.21
ns
26
(Tx) CK high to STXD valid from high impedance
9.59
17.08
7.86
15.59
ns
27a
(Tx) CK high to STXD high
9.59
17.08
7.86
15.59
ns
27b
(Tx) CK high to STXD low
9.59
17.08
7.86
15.59
ns
28
(Tx) CK high to STXD high impedance
9.59
16.84
7.86
15.35
ns
29
SRXD setup time before (Rx) CK low
2.52
2.52
ns
30
SRXD hole time after (Rx) CK low
0
0
ns
Synchronous Internal Clock Operation (SSI2 Ports)
31
SRXD setup before (Tx) CK falling
20.78
20.78
ns
32
SRXD hold after (Tx) CK falling
0
0
ns
Synchronous External Clock Operation (SSI2 Ports)
33
SRXD setup before (Tx) CK falling
4.42
4.42
ns
34
SRXD hold after (Tx) CK falling
0
0
ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
Table 31. SSI to SSI2 Ports Timing Parameters (Continued)
Ref
No.
Parameter
1.8 V
± 0.1 V
3.0 V
± 0.3 V
Unit
MinimumMaximumMinimum
Maximum
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX21
Product
Family
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