
5-V Control Timing
MC68HC908QL4 MC68HC908QL3 MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
207
17.7 5-V Control Timing
Figure 17-3. RST and IRQ Timing
Characteristic
(1)
1. V
DD
= 4.5 to 5.5 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
; timing shown with respect to 20% V
DD
and 70% V
SS
, unless otherwise
noted.
2. Values are based on characterization results, not tested in production.
3. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 t
cyc
.
Symbol
Min
Max
Unit
Internal operating frequency
f
OP
(f
BUS
)
—
8
MHz
Internal clock period (1/f
OP
)
RST input pulse width low
(2)
t
cyc
125
—
ns
t
RL
100
—
ns
IRQ interrupt pulse width low (edge-triggered)
(2)
t
ILIH
100
—
ns
IRQ interrupt pulse period
(2)
t
ILIL
Note
(3)
—
t
cyc
RST
IRQ
t
RL
t
ILIH
t
ILIL