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參數資料
| 型號： | MC88916 |
| 廠商： | Motorola, Inc. |
| 英文描述： | LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET |
| 中文描述： | 低偏移的CMOS PLL時鐘驅動器，帶有處理器復位 |
| 文件頁數： | 2/9頁 |
| 文件大?。?/td> | 114K |
| 代理商： | MC88916 |
MC88916
MOTOROLA
TIMING SOLUTIONS
BR1333 — REV 5
2
19
20
18
17
16
15
14
13
12
11
2
1
3
4
5
6
7
8
9
10
Pinout: 20–Lead Wide SOIC Package
(Top View)
GND
Q3
2X_Q
VCC
Q/2
MR
VCC
RST_IN
Q2
VCC(AN)
GND
RC1
RST_OUT(LOCK)
GND(AN)
PLL_EN
SYNC
Q1
GND
VCC
Q0
Description of the RST_IN/RST_OUT(LOCK) Functionality
(continued)
After the system start–up is complete and the 88916 is
phase–locked to the SYNC input signal (RST_OUT high), the
processor reset functionality can be utilized. When the
RST_IN pin is toggled low (min. pulse width=10nS),
RST_OUT(LOCK) will go to the low state and remain there
for 1024 cycles of the ‘Q’ output frequency (512 SYNC
cycles). During the time in which the RST_OUT(LOCK) is
actively pulled low, all the 88916 clock outputs will continue
operating correctly and in a locked condition to the SYNC
input (clock signals to the 68030/040 family of processors
must continue while the processor is in reset). A propagation
delay after the 1024th cycle RST_OUT(LOCK) goes back to
the high impedance state to be pulled high by the resistor.
Power Supply Ramp Rate Restriction for Correct 68030
Processor Reset Operation During System Start–up
Because the RST_OUT(LOCK) pin is an indicator of
phase–lock to the reference source, some constraints must
be placed on the power supply ramp rate to make sure the
RST_OUT(LOCK) signal holds the processor in reset during
system start–up (power–up). With the recommended loop
filter values (see Figure 7) the lock time is approximately
10ms. The phase–lock loop will begin attempting to lock to a
reference source (if it is present) when VCC reaches 2V. If
the VCC ramp rate is significantly slower than 10ms, then the
PLL could lock to the reference source, causing
RST_OUT(LOCK) to go high before the 88916 and 68030
processor is fully powered up, violating the processor reset
specification. Therefore, if it is necessary for the RST_IN pin
to be held high during power–up, the VCC ramp rate must be
less than 10mS for proper 68030/040 reset operation.
This ramp rate restriction can be ignored if the RST_IN pin
can be held low during system start–up (which holds
RST_OUT low). The RST_OUT(LOCK) pin will then be
pulled back high 1024 cycles after the RST_IN pin goes high.
CAPACITANCE AND POWER SPECIFICATIONS
Symbol
Parameter
Value Typ
Unit
Test Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0V
CPD
Power Dissipation Capacitance
40
pF
VCC = 5.0V
PD1
Power Dissipation at 33MHz With 50
Thevenin Termination
15mW/Output
90mW/Device
mW
VCC = 5.0V
T = 25
°
C
PD2
Power Dissipation at 33MHz With 50
Parallel Termination to GND
37.5mW/Output
225mW/Device
mW
VCC = 5.0V
T = 25
°
C
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MC88916DW | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET |
| MC88916DW70 | 功能描述:IC DRIVER CLK PLL 70MHZ 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| MC88916DW80 | 功能描述:IC DRIVER CLK PLL 80MHZ 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| MC88916DWR2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET |
| MC88916EG70 | 功能描述:IC PLL CLOCK DRIVER 20-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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