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| 型號(hào)： | MC88915TFN55 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 5/18頁(yè) |
| 文件大?。?/td> | 401K |
| 代理商： | MC88915TFN55 |
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MC88915T
38
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Figure 4. Depiction of the Fixed SYNC to Feedback Offset (tPD)
Which is Present When a 1 m
Resistor is Tied to VCC or Ground
5.
The tSKEWr specification guarantees the rising edges of
outputs Q/2, Q0, Q1, Q2, Q3, and Q4 will always fall within
a 500 ps window within one part. However, if the relative
position of each output within this window is not specified,
the 500 ps window must be added to each side of the tPD
specification limits to calculate the total part-to-part skew.
For this reason, the absolute distribution of these outputs
are provided in Table 23. When taking the skew data, Q0
was used as a reference, so all measurements are relative
to this output. The information in Table 23 is derived from
measurements taken from the 14 process lots described
in Note 1, over the temperature and voltage range.
6.
Calculation of Total Output-to-Skew Between Multiple
Parts (Part-to-Part Skew)
By combining the tPD specification and the information in
Note 5, the worst case output-to-output skew between mul-
tiple 88915s connected in parallel can be calculated. This
calculation assumes all parts have a common SYNC input
clock with equal delay of input signal to each part. This
skew value is valid at the 88915 output pins only (equally
loaded), it does not include PCB trace delays due to vary-
ing loads.
With a 1.0 M
resistor tied to analog VCC as shown in Note
4, the tPD spec. limits between SYNC and the Q/2 output
(connected to the FEEDBACK pin) are –1.05 ns and
–0.5 ns. To calculate the skew of any given output between
two or more parts, the absolute value of the distribution of
the output given in Table 23 must be subtracted and added
to the lower and upper tPD spec limits respectively. For out-
put Q2, [276 – (–44)] = 320 ps is the absolute value of the
distribution. Therefore, [–1.05 ns – 0.32 ns] = –1.37 ns is
the lower tPD limit, and [–0.5 ns + 0.32 ns] = –0.18 ns is the
upper limit. Therefore, the worst case skew of output Q2
between any number of parts is |(–1.37) – (–0.18)| =
1.19 ns. Q2 has the worst case skew distribution of any
output, so 1.2 ns is the absolute worst case output-to-out-
put skew between multiple parts.
7.
Note 4 explains the tPD specification was measured and is
guaranteed for the configuration of the Q/2 output
connected to the FEEDBACK pin and the SYNC input
running at 10 MHz. The fixed offset (tPD) as described
above has some dependence on the input frequency and
at what frequency the VCO is running. The graphs of
Figure 5 demonstrate this dependence.
The data presented in Figure 5 is from devices represent-
ing process extremes, and the measurements were also
taken at the voltage extremes (VCC = 5.25 V and 4.75 V).
Therefore, the data in Figure 5 is a realistic representation
of the variation of tPD.
EXTERNAL LOOP FILTER
330
0.1
F
RC1
R2
C1
1 M
REFERENCE
RESISTOR
ANALOG GND
With the 1.0 M
resistor tied in this fashion, the tPD
specification measured at the input pins is:
tPD = –0.775 ns ± 0.275 ns
ANALOG VCC
330
0.1
F
R2
C1
1 M
REFERENCE
RESISTOR
ANALOG GND
RC1
SYNC INPUT
FEEDBACK OUTPUT
2.25 ns OFFSET
3.0 V
5.0 V
SYNC INPUT
FEEDBACK OUTPUT
–0.775 ns OFFSET
3.0 V
5.0 V
With the 1.0 M
resistor tied in this fashion, the tPD
specification measured at the input pins is:
tPD = 2.25 ns ± 1.0 ns
Table 23. Relative Positions of Outputs Q/2, Q0–Q4, 2X_Q
Within the 500 ps tSKEWr Spec Window
Output
– (ps)
+ (ps)
Q0
0
Q1
–72
40
Q2
–44
276
Q3
–40
255
Q4
–274
–34
Q/2
–16
250
2X_Q
–633
–35
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