參數(shù)資料
型號(hào)： MC88915TFN55
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 時(shí)鐘及定時(shí)
英文描述： 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28
封裝： PLASTIC, LCC-28
文件頁(yè)數(shù)： 10/18頁(yè)
文件大?。?/td> 401K
代理商： MC88915TFN55
MC88915T
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
43
Figure 9. Representation of a Potential Multi-Processing Application Utilizing the MC88915T
for Frequency Multiplication and Low Board-to-Board Skew
MC88915T System Level Testing Functionality
Three-state functionality was added to the 100 MHz version
of the MC88915T to ease system board testing. Bringing the
OE/RST pin low will put all outputs (except for LOCK) into the
high impedance state. As long as the PLL_EN pin is low, the
Q0–Q4, Q5, and the Q/2 outputs will remain in the low state
after the OE/RST until a falling SYNC edge is seen. The 2X_Q
output is the inverse of the SYNC signal in this mode. If the
3-state functionality is used, a pull-up or pull-down resistor must
be tied to the FEEDBACK input pin to prevent it from floating
when the fed back output goes into high impedance.
With the PLL_EN pin low the selected SNC signal is gated
directly into the internal clock distribution network, bypassing
and disabling the VCO. In this mode the outputs are directly
driven by the SYNC input (per the block diagram). This mode
can also be used for low frequency board testing.
NOTE: If the outputs are put into 3-state during normal PLL
operation, the loop will be broken and phase-lock will
be lost. It will take a maximum of 10 ms (tLOCK spec)
to regain phase-lock after the OE/RST pin goes back
high.
CMMU
CPU
CMMU
2f
PLL
MC88915T
CPU
CARD
CMMU
CPU
CMMU
2f
PLL
MC88915T
CPU
CARD
CLOCK
@ f
SYSTEM
CLOCK
SOURCE
DISTRIBUTE
CLOCK @ f
CLOCK @ 2f
AT POINT OF USE
MEMORY
CONTROL
2f
PLL
MC88915T
MEMORY
CARDS
CLOCK @ 2f
AT POINT OF USE
相關(guān)PDF資料
PDF描述
MC88915TFN70 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28
MC88916DW70 88916 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO20
MC88921DW 88921 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
MC88LV915TFN 88LV SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28
MC88LV926DW 88LV SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO20
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC88915TFN70 功能描述:IC DRIVER CLK PLL 70MHZ 28-PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類(lèi)型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
MC88915TFN70R2 功能描述:IC DRIVER CLK PLL 70MHZ 28-PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類(lèi)型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
MC88916 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET
MC88916DW 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET
MC88916DW70 功能描述:IC DRIVER CLK PLL 70MHZ 20-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類(lèi)型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
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