參數(shù)資料
    型號: MC8641HX1000GB
    廠商: Freescale Semiconductor
    文件頁數(shù): 46/130頁
    文件大?。?/td> 0K
    描述: IC MPU SGL E600 CORE 994FCCBGA
    標準包裝: 1
    系列: MPC86xx
    處理器類型: 32-位 MPC86xx PowerPC
    速度: 1.0GHz
    電壓: 1.05V
    安裝類型: 表面貼裝
    封裝/外殼: 994-BCBGA,F(xiàn)CCBGA
    供應商設(shè)備封裝: 994-FCCBGA(33x33)
    包裝: 托盤
    MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
    22
    Freescale Semiconductor
    DDR and DDR2 SDRAM
    Table 15 provides the recommended operating conditions for the DDR SDRAM component(s) when
    Dn_GVDD(typ) = 2.5 V.
    Table 16 provides the DDR capacitance when Dn_GV
    DD (typ)=2.5 V.
    Table 17 provides the current draw characteristics for MVREF.
    Table 15. DDR SDRAM DC Electrical Characteristics for D
    n_GVDD (typ) = 2.5 V
    Parameter/Condition
    Symbol
    Min
    Max
    Unit
    Notes
    I/O supply voltage
    D
    n_GVDD
    2.375
    2.625
    V
    1
    I/O reference voltage
    D
    n_MVREF
    0.49
    × Dn_GVDD
    0.51
    × Dn_GVDD
    V2
    I/O termination voltage
    VTT
    D
    n_MVREF – 0.04
    D
    n_MVREF + 0.04
    V
    3
    Input high voltage
    VIH
    D
    n_MVREF + 0.15
    D
    n_GVDD + 0.3
    V
    Input low voltage
    VIL
    –0.3
    D
    n_MVREF– 0.15
    V
    Output leakage current
    IOZ
    –50
    50
    μA4
    Output high current (VOUT = 1.95 V)
    IOH
    –16.2
    mA
    Output low current (VOUT = 0.35 V)
    IOL
    16.2
    mA
    Notes:
    1. D
    n_GVDD is expected to be within 50 mV of the DRAM Dn_GVDD at all times.
    2. MVREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the receiver.
    Peak-to-peak noise on D
    n_MVREF may not exceed ±2% of the DC value.
    3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
    equal to D
    n_MVREF. This rail should track variations in the DC level of Dn_MVREF.
    4. Output leakage is measured with all outputs disabled, 0 V
    VOUT Dn_GVDD.
    Table 16. DDR SDRAM Capacitance for D
    n_GVDD (typ) = 2.5 V
    Parameter/Condition
    Symbol
    Min
    Max
    Unit
    Notes
    Input/output capacitance: DQ, DQS
    CIO
    68
    pF
    1
    Delta input/output capacitance: DQ, DQS
    CDIO
    —0.5
    pF
    1
    Note:
    1. This parameter is sampled. D
    n_GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = Dn_GVDD/2,
    VOUT (peak-to-peak) = 0.2 V.
    Table 17. Current Draw Characteristics for MVREF
    Parameter / Condition
    Symbol
    Min
    Max
    Unit
    Note
    Current draw for MVREF
    IMVREF
    500
    μA1
    1. The voltage regulator for MVREF must be able to supply up to 500 μA current.
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