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參數(shù)資料
| 型號： | MC80C52CXXX-16 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁數(shù)： | 15/46頁 |
| 文件大?。?/td> | 4720K |
| 代理商： | MC80C52CXXX-16 |
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21
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
Table 6-3.
Selection of Main Clock
To avoid unintentional switching of main clock source, a protected change sequence must be followed to change the
CLKMS bits, as follows:
1.
Write the signature for change enable of protected I/O register to register CCP
2.
Within four instruction cycles, write the CLKMS bits with the desired value
6.5.2
CLKPSR – Clock Prescale Register
Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system clock. These bits can be
written at run-time to vary the clock frequency and suit the application requirements. As the prescaler divides the master
clock input to the MCU, the speed of all synchronous peripherals is reduced accordingly. The division factors are given in
Table 6-4.
Clock Prescaler Select
CLKM1
CLKM0
Main Clock Source
0
Calibrated Internal 8 MHz Oscillator
0
1
Internal 128 kHz Oscillator (WDT Oscillator)
1
0
External clock
1
Reserved
Bit
7
6
5
4
3
2
1
0
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
CLKPSR
Read/Write
R
R/W
Initial Value
0
1
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Clock Division Factor
0
1
0
1
2
0
1
0
4
0
1
8 (default)
0
1
0
16
0
1
0
1
32
0
1
0
64
0
1
128
1
0
256
1
0
1
Reserved
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