參數(shù)資料
型號: MC74HCU04ADTR2G
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Hex Unbuffered Inverter High−Performance Silicon−Gate CMOS
中文描述: HC/UH SERIES, HEX 1-INPUT INVERT GATE, PDSO14
封裝: LEAD FREE, TSSOP-14
文件頁數(shù): 3/9頁
文件大?。?/td> 177K
代理商: MC74HCU04ADTR2G
MC74HCU04A
http://onsemi.com
3
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Derating — Plastic DIP: –10mW/ C from 65 to 125 C
SOIC Package: –7mW/ C from 65 to 125 C
TSSOP Package:
6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High
Speed CMOS Data Book (DL129/D).
SOIC Package
500
stg
Symbol
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
Parameter
Min
Max
6.0
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
V
CC
+ 125
V
T
A
0
No
V
Operating Temperature, All Package Types
– 55
C
t
r
, t
f
Input Rise and Fall Time (Figure 1)
ns
Symbol
2.4 mA
125 C
Parameter
Test Conditions
V
CC
V
– 55 to
25 C
85 C
Unit
V
IH
Minimum High
Level Input
V
= 0.5 V*
2.0
4.5
6.0
1.7
3.6
4.8
1.7
3.6
4.8
l.7
3.6
4.8
V
V
IL
Maximum Low
Level Input
V
out
= V
CC
– 0.5 V*
2.0
4.5
0.3
0.3
0.3
V
OH
in
6.0
5.5
5.5
5.5
out
5.26
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high
impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
(V
in
or V
out
)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
V
CC
.
相關(guān)PDF資料
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MC74HCU04ANG Hex Unbuffered Inverter High−Performance Silicon−Gate CMOS
MC74LCX00DR2 Low-Voltage CMOS Quad 2-Input NAND Gate
MC74LCX00DR2G Low-Voltage CMOS Quad 2-Input NAND Gate
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